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[VHDL-FPGA-Verilog] cpu-kongzhi

Description: 1. 实现能够执行R型、LW、SW、BEQ以及J指令的单时钟控制器，使其能够支持基本的指令。 2. 用Verilog HDL实现单时钟CPU控制器，在ISE上进行波形仿真，并在FPGA上实现。-1. Implementations can perform R-type, LW, SW, BEQ, and J instruction every clock controller, to enable them to support the basic directives. 2 single-clock with Verilog HDL CPU controller, the ISE on the waveform simulation and FPGA implementation.
Platform: | Size: 1024 | Author: dino | Hits:

[Mathimatics-Numerical algorithms] lw

Description: 这是个用Richtmyer格式编写的源代码，在输入初始条件后，可以用来求解rieman问题的数值解-This is a Richtmyer format with the input source code, after input the initial conditions, can be used to solve the numerical solution of the rieman problem
Platform: | Size: 2048 | Author: 唐小军 | Hits:

[Mathimatics-Numerical algorithms] lw.

Description: 这是个用Richtmyer格式加入了人工粘性项编写的源代码，输入初始条件后，可以用来求解rieman问题的数值解-This is a Richtmyer format of the source code with artificial viscosity , after input the initial conditions, can be used to solve the numerical solution of the rieman problem
Platform: | Size: 2048 | Author: 唐小军 | Hits:

[SCM] clock-lw

Description: 2010年电子信息工程本科毕业论文，利用单片机的设计制作一个数字钟，详细阐述了数字钟的工作原理，讨论了硬件电路中各个模块的实现方法，并对它们进行了严格的理论逻辑推敲和实验测试，以达到设计要求。它可以实现数字钟的基本功能以及温度检测、定时自动闹铃等功能，而且具有更高的准确性。而这些，都是以数字化为基础的，因此研究单片机语言以及扩大其应用，有着非常现实的意义。-2010 Electronic and Information Engineering undergraduate thesis, the use of single-chip design a digital clock, digital clock elaborated works, discussed the hardware circuit implementation of each module, and they conducted a rigorous logical scrutiny theoretical and experimental tests to meet the design requirements. It can achieve the basic functions of the digital clock and temperature detection, regular automatic alarm functions, and has a higher accuracy. These are the numbers into the basis, the study of language and expand its microcontroller applications, has a very real sense.
Platform: | Size: 277504 | Author: 董云鹏 | Hits:

[matlab] lw

Description: 运用matlab对管道进行传热计算的基础程序-Pipe heat transfer calculation
Platform: | Size: 1024 | Author: 吴薇 | Hits:

[VHDL-FPGA-Verilog] multi_cycle_Verilog

Description: this code has written in verilog and it is about multi cycle mips processor .This code can do alot of jobs for examole,add ,addi ,addiu,and ,andi,ori ,mfhi.mfho,xor,slt,slti,ssw,lw,lui ,jal ,mult ,multu,... and it can multiply two input inter less than 32 bits in 32 clocks .
Platform: | Size: 4096 | Author: sajad | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[VHDL-FPGA-Verilog] MIPS-processor-Verilog-code

Description: 原创，MIPS处理器Verilog源码，在FPGA实现单周期MIPS处理器，实现存储访问指令load word(lw)和store word(sw)，算术逻辑指令add、addi、sub、and、or和slt跳转指令branch equal(beq)和jump(j)-Original, achieves single-cycle MIPS processor MIPS processor Verilog source code, the FPGA, storage access instructions load word (lw) and store word (sw) arithmetic logic instructions add, addi, sub, and, or, and slt jump instructionbranch equal (beq, which) and jump (j)
Platform: | Size: 7168 | Author: ZLS | Hits:

[VHDL-FPGA-Verilog] PipelineCPU

Description: 用Verilog HDL语言或VHDL语言来编写，实现多周期CPU设计。能够完成以下二十二条指令。（均不考虑虚拟地址和Cache，并且默认为大端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd，rt，rs sra rd，rt，shamt blez rs, imm j target lwl rt，offset（base） lwr rt，offset（base） lw rt，imm（rs） sw rt，imm（rs） -Written in Verilog HDL or VHDL language, multi-cycle CPU design. Able to complete the following 22 instructions. (Not taking into account the virtual address and the Cache, and the default is big endian): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)
Platform: | Size: 5079040 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] mulitcpu

Description: 用verilog HDL语言或者VHDL语言来编写，实现多时钟周期CPU的设计。能够完成以下二十二条指定（均不考虑虚拟地址和Cache，并且默认为小端方式）： add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset(base) lwr rt, offset(base) lw rt, imm(rs) sw rt, imm(rs) -Verilog HDL language or VHDL language to write multi-clock cycle of the CPU design. To complete the following 22 specified (not taking into account the virtual address and the Cache and the default Xiaoduan): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt of nor rd, rs, rt xori rt, rs, imm clo clz slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwr rt, offset (base) lw rt, imm (rs) sw rt, imm (rs)Undo edits DictionaryGoogle Translate for Business:Translator ToolkitWebsite TranslatorGlobal Market Finder
Platform: | Size: 8877056 | Author: 徐帆 | Hits:

[VHDL-FPGA-Verilog] a

Description: mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions-mips single cycle verilog code for add,sub,bne,slt,lw,sw,xori instructions
Platform: | Size: 8192 | Author: nhan | Hits:

[assembly language] DSP_mutipile_MIPS_CPUcode

Description: 32位多周期MIPS微处理器设计代码。具体功能：运行下列的6类32条MIPS32指令。算术运算指令：ADD、ADDU、SUB、SUBU、ADDI、ADDIU。逻辑运算指令：AND、OR、NOR、XOR、ANDI、ORI、XORI、SLT、SLTU、SLTI、SLTIU。移位指令：SLL、SLLV、SRL、SRLV、SRA。条件分支指令：BEQ、BNE、BGEZ、BGTZ、BLEZ、BLTZ。无条件跳转指令：J、JR。数据传送指令：LW、SW。 -Multi-cycle MIPS microprocessor design code
Platform: | Size: 15360 | Author: 姬一 | Hits:

[File Format] Novel-approach-for-texture

Description: 为提高基于内容的图像检索系统中纹理特征提取的有效性,提出了又一种纹理图像检索方法。该方法利用非下采样 Contourlet变换对图像进行分解, 提取不同子带和不同方向变换系数矩阵的均值和方差为特征向量, 作为数据库中纹理图像的索引,并利用两种不同的相似度函数计算图像之间的相似度,建立了一套基于示例查询图像的纹理图像检索系统。实验结果表明,与小波包等特征提取方法相比, 该方法不仅能降低特征向量维数,而且能取得更高的检索准确率和检索速度。-To i ncrease t he vali d ity o f tex t ure feature ex tracti on in conten t-based i mage retrieva l syste m, a nove l approach for tex ture i m age retr ieva lw as proposed . Th i s approach w as based on theNonSubsamp l ed Con t our l et T ransform ( NSCT). The m eans and variab l es of NSCT co efficien tsm a trix i n d ifferen t s ubbands and var i ous directi ons were ex tracted to for m the feature vectors wh ich we re reg arded as i ndexes of tex t ure i mages i n i m age da tabase . Two s i m il ar ity functi ons were used to compute the si m ilar i ty bet w een i m ages . A tex ture re trieval sy stem based on query i m age w as deve l oped . Co m pared to the w ave let packag e transform, th i s approach can no t on l y reduce the di m ension o f feature vectors , but a l so get higher accu racy and speed of retr i eva. l
Platform: | Size: 346112 | Author: jjdjjf | Hits:

[Industry research] A200802-199

Description: LW-IGMPv3 协议在XORP 平台上的分析与实现
Platform: | Size: 398336 | Author: velvin1978 | Hits:

[SCM] AN332Ver0.2

Description: 本资料包涵Si4704/05/06/1x/2x/3x/4x资料，及驱动程序，应用实例-This document provides an overview of the programming requirements for the Si4704/05/06/1x/2x/3x/4x FM transmitter/AM/FM/SW/LW/WB receiver. The hardware control interface and software commands are detailed along with several examples of the required steps to configure the device for various modes of operation.
Platform: | Size: 1482752 | Author: xuxiao | Hits:

[Other] Sdspectrum

Description: 具有噪音检验的一维序列x(n)的离散功率谱分析，ol(lw)频率，tl(lw)周期，sl(lw)离散功率谱，st95(lw)红噪音或白噪音谱的95 置信上限，其中lw=[n/2.]。-The discrete power spectral analysis of the one-dimensional sequence x (n) having a noise testing, 95 of the frequency of OL (LW), TL (LW) cycles, SL (LW) discrete power spectrum ST95 (LW), the red noise or white noise spectrum upper confidence limit, wherein LW = [n/2].
Platform: | Size: 1024 | Author: brief | Hits:

[VHDL-FPGA-Verilog] lw

Description: 实现抢答器的功能，四人抢答，还有附加功能包括抢答计时，提前抢答预警，到时间停止，记录分数等-you can see
Platform: | Size: 4096 | Author: 陶轩 | Hits:

[Program doc] LW

Description: 各种定位算法的详细说明，有详细的推导过程，并提出了两种TDOA_AOA混合算法。-A detailed description of the various positioning algorithm, detailed derivation process and proposed two TDOA_AOA hybrid algorithm.
Platform: | Size: 1974272 | Author: 王子任 | Hits:

[JSP/Java] 01

Description: 本程序使用的是MySQL数据库，读者可以参考光盘使用说明书中的步骤导入源代码并配置数据库。运行com.lw.frame包中的MainFrame类，启动程序。-This program uses a MySQL database, the reader can refer to the disc manual steps to import the source code and configuration database. Run com.lw.frame package MainFrame class, start the program.
Platform: | Size: 759808 | Author: 张张 | Hits:

[SQL Server] 02

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