Welcome![Sign In][Sign Up]
Location:
Search - lw

Search list

[Embeded-SCM Developuip_webserver-changed

Description: lpc2478 + DP83848 的网口程序,本人亲自调通并测试通过-lpc2478+ DP83848 The net interface program, personally and test through general adjustment.
Platform: | Size: 587776 | Author: 梁树 | Hits:

[Internet-NetworkLW-IGMPv3-20080107

Description:
Platform: | Size: 38912 | Author: yfchou | Hits:

[Other systemsBYSJ-lyglxt

Description: 毕业设计(旅游管理系统)源码+毕业设计论文-BYSJ+LW
Platform: | Size: 665600 | Author: jiangl | Hits:

[VHDL-FPGA-VerilogPIPE_LINING_CPU_TEAM_24

Description: 采用Quatus II编译环境,使用Verilog HDL语言编写实现了五段流水线CPU。 能够完成以下二十二条指令(均不考虑虚拟地址和Cache,并且默认为小端方式): add rd,rs,rt addu rd,rs,rt addi rt,rs,imm addiu rt,rs,imm sub rd,rs,rt subu rd,rs,rt nor rd,rs,rt xori rt,rs,imm clo rd,rs clz rd,rs slt rd,rs,rt sltu rd,rs,rt slti rt,rs,imm sltiu rt,rs,imm sllv rd,rt,rs sra rd,rt,shamt blez rs,imm j target lwl rt,offset(base) lwl rt,offset(base) lw rt,imm(rs) sw rt,imm(rs) 在本设计中,采取非常良好的模块化编程风格,共分十三个主要模块PIPE_LINING_CPU_TEAM_24.v为顶层实体文件,对应为PIPE_LINING_CPU_TEAM_24模块作为顶层实体模块,如下: ifetch.v、regdec.v、exec.v、mem.v、wr.v分别实现五个流水段; cpuctr.v用于产生CPU控制信号; ALU.v用于对操作数进行相应指令的运算并输出结果; DM.v数据存储器 IM.v指令存储器 datareg.v数据寄存器堆 extender.v位扩展 yiwei_32bits.v 实现32位四种移位方式的移位器 在顶层实体中,调用ifetch.v、regdec.v、exec.v、mem.v、wr.v这五个模块就实现了流水线CPU。顶层模块的结构清晰明了。对于学习verilog编程非常有用- Quatus II compiled by the environment, using Verilog HDL language to achieve a five-stage pipeline CPU. To complete the following 22 commands (not considering the virtual address and Cache, and the default mode for the small end): add rd, rs, rt addu rd, rs, rt addi rt, rs, imm addiu rt, rs, imm sub rd, rs, rt subu rd, rs, rt nor rd, rs, rt xori rt, rs, imm clo rd, rs clz rd, rs slt rd, rs, rt sltu rd, rs, rt slti rt, rs, imm sltiu rt, rs, imm sllv rd, rt, rs sra rd, rt, shamt blez rs, imm j target lwl rt, offset (base) lwl rt, offset (base) lw rt, imm (rs) sw rt, imm (rs) In this design, take a very good modular programming style, is divided into 13 main modules PIPE_LINING_CPU_TEAM_24.v for the top-level entity file, the corresponding module as a top-level entity for the PIPE_LINING_CPU_TEAM_24 modules, as follows: ifetch.v, regdec.v, exec.v, mem.v, wr.v water were to achieve the five paragraph cpuctr.v used to generate CPU control signal ALU.v accordingly
Platform: | Size: 4946944 | Author: | Hits:

[Documentslw

Description: 本压缩包涵盖了4个基于s3c2410 arm9开发板的相关论文 -The archive covers four s3c2410 arm9 development board based on the relevant papers
Platform: | Size: 1167360 | Author: 郑博夫 | Hits:

[VHDL-FPGA-Verilogxapp1026

Description:
Platform: | Size: 5367808 | Author: zyb | Hits:

[ARM-PowerPC-ColdFire-MIPSLwip-1.3.0-to-LPC2106-ENC28J60-and-Proteus.RAR

Description: 移植Lwip-1.3.0到LPC2106+ENC28J60及其Proteus仿真-Transplantation Lwip-1.3.0 to the LPC2106+ ENC28J60 and Proteus simulation
Platform: | Size: 1848320 | Author: 邓宜宾 | Hits:

[VHDL-FPGA-VerilogsingleCycleProc

Description: 简化的单时钟循环VHDL处理器.可以运行一些简单的mips指令,例如add, sub, and, or, slt, beq and j. -A simplified single cycle processor in VHDL. This processor can continuously execute some simple MIPS instructions which are lw, sw, add, sub, and, or, slt, beq and j.
Platform: | Size: 191488 | Author: 糖醋鱼 | Hits:

[Com PortNet2USART

Description: STM32+LWIP的串口转网口程序源码-STM32+ LWIP switch network serial port source code
Platform: | Size: 5856256 | Author: zf | Hits:

[SCMLwIP

Description: code c for adc conversion with renesas m16c microchip
Platform: | Size: 494592 | Author: zz | Hits:

[matlablw

Description: 特征值的提取方式 有需要的可以下载试试 还不错-for the value
Platform: | Size: 1024 | Author: 甄熙 | Hits:

[Otheruu

Description: Fuzzyvlandslide susceptibility for fuzzy rule base lw
Platform: | Size: 423936 | Author: aghababaee | Hits:

[uCOS2440_ucosii_ucgui_lwip

Description: KEIL arm MDK 下移植成功2440硬件的LWIP网络程序 KEIL arm MDK 下移植成功2440硬件的LWIP网络程序 -KEIL arm MDK 2440 under the successful transplantation of hardware LWIP network program KEIL arm MDK 2440 under the successful transplantation of hardware LWIP network program
Platform: | Size: 987136 | Author: 劳巴里 | Hits:

[Special Effectslw

Description: 画函数图像,有正弦函数,二次函数,高次函数,并带有求面积, 求解-print
Platform: | Size: 34816 | Author: tan | Hits:

[SCMECAT-LW-1V-350-20071024

Description: 联网器。存在多个分区时,联网器完成各个小区之间的链接,完成监控中心对各个小区的控制-Networking devices. Multiple partitions, each network device to complete the link between the community, complete monitoring of each cell' s control center
Platform: | Size: 9216 | Author: wuzhifang | Hits:

[Windows Developdanbofangcheng

Description: 单波方程的数值解,采用L-F,矩形,L-W以及半隐错点格式求解单波方程,初边值条件自定-The numerical solution of a single wave equation, the use of LF, rectangular, LW, and the wrong point scheme for solving semi-implicit single wave equation, initial and boundary conditions from the set
Platform: | Size: 18432 | Author: 也罢 | Hits:

[DirextX123123DirectShow

Description: 基于DirectShow视频帧实时捕捉的设计与实现 主要针对远程教育等软件系统中现存的􀀂 黑屏 问题提出一种解决方案。运用D irectShow 技术对多媒体文件或多媒体流 中的视频流进行处理, 实现从多媒体文件视频流中进行视频帧的实时捕获, 而后调用W indow s中GDI函数对获取的图像帧进行渲 染, 最后按照M PEG2标准合成AVI视频文件并可以实时重放。-In this pape r, w e present a so lution to reso lve the .. black screen problem occurred in softw are sy stem such as distance education, etc. Firstly, w e imp lem ent the v ideo..fram es rea l..tim e capturing from v ideo stream ofm ultim edia files by using D irectShow technology to dea lw ith mu ltim ed ia files or v ideo stream in mu ltimed ia stream. Then, the GDI function o fW indow s is invoked to render the im ag e fram es, wh ich are captured by the DirectShow. Fina lly, acco rd ing to the standard o fMPEG2 a file is com posed in AVI v ideo fo rm at wh ich is able to replay rea l..tim ely.
Platform: | Size: 1794048 | Author: zhu | Hits:

[ELanguagefanhuibian

Description: 用C写的反汇编程序: 举例: Input the instructions ended with @: LW $T1, 0($A0) ADD $T0, $ZERO, $ZERO R0: ADDi $T0, $ZREO, 1 SLT $T2, $T0, $A1 BEQ $T2, $ZERO, RR ADD $T2, $T0, $A0 LW $T2, 0($T2) ADD $T1, $T1, $T2 J R0 RR: ADD $V0, $T1, $ZERO JR $RA @ 00000000: 8c890000 00000004: 00004020 00000008: 20080001 0000000c: 0105502a 00000010: 11400004 00000014: 01045020 00000018: 8d4a0000 0000001c: 012a4820 00000020: 08000002 00000024: 01201020 00000028: 03e00008 Press any key to continue-disassembling program with C
Platform: | Size: 232448 | Author: tt | Hits:

[VHDL-FPGA-Verilogcpu

Description: 以ISE为平台设计的单时钟CPU,实现最基本的5条指令(R、LW、SW、BEQ、J) -ISE as a platform to design single-clock CPU, 5 to achieve the most basic instructions (R, LW, SW, BEQ, J)
Platform: | Size: 2595840 | Author: 熊思源 | Hits:

[TCP/IP stacklwip-1.4.0

Description: 一个轻量级的tcp/ip协议栈,适合用于嵌入式开发,此为2011 05 最新版本,对嵌入式以太网开发很有帮助-A lightweight tcp/ip protocol stack suitable for embedded development, this is the latest version of 201 105, is helpful for the development of embedded Ethernet
Platform: | Size: 614400 | Author: zhangyujun | Hits:
« 1 2 3 45 6 7 »

CodeBus www.codebus.net