Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - m sequence verilog

Search list

[Other] m序列

Description: Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
Platform: | Size: 4913 | Author: 张林 | Hits:

[VHDL-FPGA-Verilog] pseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[Other] m序列

Description: Verilog编写的M序列发生器，希望能对大家带来帮助。 -Verilog prepared by the M-sequence generator, we hope to bring help.
Platform: | Size: 5120 | Author: 张林 | Hits:

[VHDL-FPGA-Verilog] pn

Description: 用Verilog语言生成7位的小m序列，产生pn码-Verilog language used to generate seven small m sequence code generated pn
Platform: | Size: 2048 | Author: 楚鹤 | Hits:

[matlab] PN_Generator

Description: 用Verilog编写的一个简单的产生伪随机序列的代码（m序列），比较实用。-Verilog prepared with the emergence of a simple pseudo-random code sequence (m sequence), more practical.
Platform: | Size: 116736 | Author: 龚阳 | Hits:

[VHDL-FPGA-Verilog] verilog_m

Description: 用verilog生成的m序列，包含四个.v的文件-verilog m sequence
Platform: | Size: 6144 | Author: priscilla | Hits:

[VHDL-FPGA-Verilog] cml

Description: 基于Verilog的数字基带通信系统 3. 项目描述：本系统为通信原理课程设计课题之一，用Verilog语言编写数字基带通信系统的应用程序，完成P=31的m序列的生成，并进行HDB3编码传输，在接收端进行译码接收。-Verilog-based digital baseband communication system 3. Project Description: The system is one of the topics Communication Theory course design, using Verilog language digital baseband communication system applications, the completion of P = 31 m-sequence generation, and make HDB3 coded transmission, reception at the receiving end for decoding.
Platform: | Size: 253952 | Author: chengmengli | Hits:

[VHDL-FPGA-Verilog] hamming_encodeadecode

Description: 用Verilog语言编写的对m序列进行汉明码编译码的程序。具体实现为产生m序列后对其进行(7,4)汉明码编码并加错，然后将其纠错译码并输出，详细过程见仿真。-Written by Verilog m sequence of procedures for coding and decoding Hamming codes. Concrete realization of m sequence to produce its (7,4) hamming code and a mistake, and then error correction decoding and output, see the detailed process simulation.
Platform: | Size: 308224 | Author: 周杰奏 | Hits:

[VHDL-FPGA-Verilog] BPSK

Description: 用于BPSK调制的自行设计，说明如下： 1.matlab.txt中的程序是matlab平台下的.mat格式。目的是输出一个64*4的矩阵，矩阵的每个元素都为0~255间的整数。矩阵每行的四个数是一个码元的四个抽样点的量化值。但由于当前码元通过升余弦滤波系统时，受到前后共6个码元的共同影响，所以是由6个码元共同决定。这6个码元是随机的，可能是0也可能是1（双极性时可能是-1也可能是+1），故6个码元共2^6=64种情况，所以产生的矩阵是64*4。最后逐行输出这256个数。 2.BPSK3中程序的目的是：将m序列通过滚降系数为0.3的升余弦滤波系统后的信号采样输出。 3.BPSK5中程序的目的是：将m序列通过滚降系数为0.5的升余弦滤波系统后的信号采样输出。 4.以上两个程序的运行平台为Quartus（verilog语言）。-BPSK modulation is used to design, as follows: 1.matlab.txt the program is under matlab platform. Mat format. Purpose is to output a 64* 4 matrix, each element is an integer between 0 and 255. Matrix of each line is a symbol of four the number of sampling points of the four quantitative value. However, due to the current symbol by raised cosine filtering system, before and after a total of six yards by the combined effect of element, it is shared by the six yards per decision. The 6 symbol is random, may be 0 may be 1 (may be bipolar may be+1-1), so a total of six yards per 2 ^ 6 = 64 kinds of situations, so the resulting matrix 64* 4. Finally, the number of progressive output of the 256. 2.BPSK3 purposes of the procedure is: m sequence of roll-off factor of 0.3 by the raised cosine filter system output after the signal sampling. 3.BPSK5 purposes of the procedure is: m sequence of roll-off factor of 0.5 by the raised cosine filter system output after the signal sampling.
Platform: | Size: 4096 | Author: | Hits:

[VHDL-FPGA-Verilog] Verilog----m

Description: verilog 编写的m 序列，可以直接使用。-verilog written m-sequence can be used directly.
Platform: | Size: 41984 | Author: 宫晓鹏 | Hits:

[VHDL-FPGA-Verilog] m-xulie

Description: 频率可步进M序列发生器 从10K 到100K ,步进为10K VERILOG编写-M-sequence generator frequency step from 10K to 100K, the preparation step for the 10K VERILOG
Platform: | Size: 5739520 | Author: 王新 | Hits:

[VHDL-FPGA-Verilog] MSequenceGenerator

Description: 5位的M序列发生器，verilog代码实现。5次本原多项式采用f(x)=x^5+x^2+1-5 of the M-sequence generator, verilog code. 5 using a primitive polynomial f (x) = x ^ 5+ x ^ 2+1
Platform: | Size: 109568 | Author: 陈振睿 | Hits:

[VHDL-FPGA-Verilog] m_ca7

Description: verilog编写的基于CA算法的m序列发生器，其中验证了多种CA系数来实现m序列。-CA-based algorithm written in verilog m-sequence generator, which verify the CA factor to achieve a variety of m-sequence.
Platform: | Size: 19456 | Author: 夏洛 | Hits:

[VHDL-FPGA-Verilog] Verilog-Mxulie

Description: 用Verilog编的M序列代码，用的是移位发生器的思想，即循环移动并用后来的数值取代-M-sequence code in Verilog code, using the shift generator the idea that the circulation moving and replaced with the later values
Platform: | Size: 6144 | Author: kongxiangw | Hits:

[Other] mxulie

Description: m序列的verilog代码以及测试程序，希望对大家有用哦，花了时间写的-m sequence Verilog code, and test procedures in the hope of everyone Oh, it took time to write
Platform: | Size: 2048 | Author: 黄晓 | Hits:

[Other] m-sequence-of-pseudo-random-noise

Description: 基于verilog 的用于通信系统的m序列伪随机噪声，可综合，我已验证通过。-Based on the verilog for m-sequences of pseudo-random noise of the communication system, can be integrated, I verified through.
Platform: | Size: 14336 | Author: 张阳 | Hits:

[VHDL-FPGA-Verilog] m-sequence_gen

Description: m序列生成verilog代码，经过仿真测试，绝对可用，带仿真说明-M sequence generated Verilog code, after the simulation test, absolutely available, with the simulation
Platform: | Size: 232448 | Author: zyy | Hits:

[VHDL-FPGA-Verilog] weimafashengqi-achieved-by-verilog

Description: 该代码用Verilog语言实现了M序列的伪码产生，伪码特征方程为X13 +X7+X5+1，已通过仿真验证。-The code in Verilog realize the M-sequence pseudo-code generation, pseudo-code characteristic equation for the X13+ X7+ X5+ 1, it has been verified by simulation.
Platform: | Size: 3072 | Author: daruili | Hits:

[VHDL-FPGA-Verilog] m-Sequence

Description: FPGA,verilog,输出M序列，已调试成功，可直接在Quartus上打开。-FPGA, verilog, output M sequence, has been successfully debugged, can be opened directly on the Quartus.
Platform: | Size: 5117952 | Author: 秦枫 | Hits:

[Other] mcode

Description: 附有m码产生verilog文件和测试文件，以及详细说明。读者可根据说明配置任意级m序列发生器(With M code, Verilog files and test files are produced and detailed. The reader can configure an arbitrary m sequence generator according to the instructions)
Platform: | Size: 73728 | Author: FPGA进阶之路 | Hits:
« 12 »

CodeBus www.codebus.net