Search - matlab dpll

Search - matlab dpll - List

[Console] dpll界面程序 DL : 0: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Update : 2008-10-13 Size : 3.99kb Publisher : zhangfj_99
[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Update : 2025-02-19 Size : 122kb Publisher : 于洪彪
[matlab] DPLL DL : 1: 数字锁相环DPLL实例程序，帮助理解PLL的结构和详细原理-DPLL DPLL examples of procedures to help understand the structure and PLL detailed Principle
Update : 2025-02-19 Size : 1kb Publisher : 李向坤
[Console] dpll界面程序 DL : 0: matlab 5.3中菜单unicontrol设计中如何传递变量。本人写了一个非常简单的界面程序，请大家帮忙建评一下一下。-menu design unicontrol how to pass variables. I wrote a very simple interface program, we help build commentary about what.
Update : 2025-02-19 Size : 4kb Publisher :
[Books] 复件数字锁相环程序 DL : 0: 数字锁相环DPLL源程序，用cpld编写，展开后文件比较多，大家请耐心使用。谢谢，多多支持-DPLL source with cpld prepared after the start of more documents, please use patience. Thank you, the generous support!
Update : 2025-02-19 Size : 118kb Publisher :
[matlab] DPLL1lp DL : 0: 频带数字通信中，频带一阶锁相环simulink模型-band digital communications, a frequency band PLL Simulink model
Update : 2025-02-19 Size : 8kb Publisher : rossi
[Books] 060107[1].pdf DL : 0: 全数字锁相环,包括ＤＰＤ，ＤＬＦ，ＤＣＯ．-DPLL, including the DPD, DLF, the making.
Update : 2025-02-19 Size : 87kb Publisher : 熊静
[RFID] digitalPLL DL : 0: 数字锁相环实现源码，有很大的参考价值。由鉴相器模K加减计数器脉冲加减电路同步建立侦察电路模N分频器构成.-DPLL realize source, has a great reference value. By the phase detector counter modulus K addition and subtraction circuit synchronous pulse addition and subtraction to establish surveillance mode N divider circuit constituted.
Update : 2025-02-19 Size : 2kb Publisher : sharny
[Applications] dpll DL : 1: 数字锁相环，采用costas环的数字形式，实现跟踪载波相位，-Digital phase-locked loop, using the digital form costas loop to achieve carrier phase tracking,
Update : 2025-02-19 Size : 1kb Publisher : lily
[Windows Develop] dpll DL : 0: Quantization effect on a 2nd order DPLL design When quantization resoultion b varies, the DPLL has different outputs. This difference can be seen from step response, sine and other inputs (chirp as illustrative example).
Update : 2025-02-19 Size : 1kb Publisher : dairy
[matlab] 11112323 DL : 0: 基于锁相环Top-down的建模方法在MATLAB环境下建立数字锁相环完整的仿真模型，并用SIMULINK对数字锁相环的仿真模型进行仿真。　-Top-down phase-locked loop based on the modeling method in MATLAB environment DPLL set up a complete simulation model, and use of digital phase-locked loop SIMULINK simulation model simulation.
Update : 2025-02-19 Size : 194kb Publisher : 王利华
[3G develop] dpll DL : 0: DPLL SIMULATION in MATLAB
Update : 2025-02-19 Size : 1kb Publisher : Bhavin
[Other] PLL_grt_rtw DL : 0: C语言实现了数字锁相环的程序，不过程序比较复杂，得参照MATLAB中 Discrete 3-phase pll模型-C language implementation of the DPLL procedure, but more complicated procedures, may refer to MATLAB, Discrete 3-phase pll model
Update : 2025-02-19 Size : 24kb Publisher : 蔡科
[DSP program] dpll DL : 0: Digital Phase Locked Loop M-File
Update : 2025-02-19 Size : 1kb Publisher : bumclouds2
[matlab] dpll DL : 0: 应用matlab设计D触发器型的锁相环的设计的程序并对相位很频率进行性能图形比较-matlab desire Dpll
Update : 2025-02-19 Size : 1kb Publisher : 赵红玉
[matlab] dpll_m DL : 0: DPLL implementation in matlab
Update : 2025-02-19 Size : 1kb Publisher : p2p001
[matlab] dpll DL : 0: 数字锁相环，这里有个例子，可以借鉴看看，用simulink搭建的-dpll
Update : 2025-02-19 Size : 11kb Publisher : Shane
[Communication] Untitled8 DL : 0: source code and matlab code for second order dpll in digital signal processor
Update : 2025-02-19 Size : 1kb Publisher : nithi
[Software Engineering] Matlab-about-pll DL : 1: 。在总结前人提出的一些锁相环仿真模型的基础上,用Matlab 语言构建了一种新的适用于全数字锁相环的仿真模型对全数字锁相环版图进行了SPICE 仿真,与该模型的仿真结果相验证。-. Built using Matlab language summary of some of the previously proposed phase-locked loop simulation model based on a simulation model of a new applicable to all-digital phase-locked loop DPLL layout SPICE simulation, with the The model simulation results verified.
Update : 2025-02-19 Size : 253kb Publisher : dashu
[matlab] pll DL : 0: 基于matlab的数字pll实现，鉴相器，滤波器以及压控震荡器组成，具备良好的锁相功能，适合入门学习(Digital PLL based on MATLAB, phase detector, filter and voltage controlled oscillator, phase lock function has good, suitable for beginners to learn)
Update : 2025-02-19 Size : 17kb Publisher : qiya2

« 12 »