Search - mips cpu vhdl

[ARM-PowerPC-ColdFire-MIPS] mips_creative

Description: 一个完整的MIPS CPU，创新设计，浙江大学某学生作品，有完整的说明文档、仿真文件和测试文件，可以直接综合和仿真。-a complete MIPS CPU, innovative design, a student of Zhejiang University works with complete documentation, simulation and test documents, and can be directly integrated simulation.
Platform: | Size: 1866752 | Author: 梁文锋 | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[ARM-PowerPC-ColdFire-MIPS] or2000

Description: 这是一个MIPS架构的开发的CPU软核OR2000，比OR1200更高的版本，里面还有SOC程序，多次MPW流片成功-This is a MIPS architecture to develop the CPU soft-core OR2000, higher than OR1200 version, there is also SOC procedures, many times MPW silicon success
Platform: | Size: 102400 | Author: liming | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 简单的16位CPU的VHDL设计 vhdl代码和cpu设计过程-Simple 16-bit CPU design of the VHDL code and VHDL design process cpu
Platform: | Size: 1488896 | Author: kilva | Hits:

[ARM-PowerPC-ColdFire-MIPS] mips3

Description: modelsim+dc开发的4级流水线结构的MIPS CPU，完成基本的逻辑运算和跳转。测试程序为希尔排序，结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the results correctly.
Platform: | Size: 307200 | Author: 杨春 | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPStest00

Description: 簡易MIPS CPU程式碼此CPU包含 shift add sub and or stl beq lw sw 等功能-Simple MIPS CPU code for this CPU contains shift add sub and or stl beq lw sw functions
Platform: | Size: 7168 | Author: chen | Hits:

[Embeded-SCM Develop] IP_CORES

Description: IC内核的设计源码！其中包含MP3内核，CPU内核，I2C内核等多达式种IC设计的源码！-IC design of the kernel source code! MP3 contains one of the kernel, CPU core, I2C kernel up-type species such as IC design source!
Platform: | Size: 27160576 | Author: hehuilong | Hits:

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

Description: MIPS CPU设计实例的完整文档，台湾一个大学生的MIPS CPU完整设计文档，内附设计代码。-a complete document of MIPS CPU design , a Taiwan university students complete MIPS CPU design document, containing the design code.
Platform: | Size: 918528 | Author: 李皓 | Hits:

[VHDL-FPGA-Verilog] mips1

Description: Verilog MIPS design. I found it somewhere on Internet and it is working :-Verilog MIPS design. I found it somewhere on Internet and it is working :))))
Platform: | Size: 18432 | Author: Asparuh Grigorov | Hits:

[Other] cpu

Description: 基于MIPS指令集的32位CPU设计与VHDL实现-Based on the MIPS instruction set of the 32-bit CPU design and the realization of VHDL
Platform: | Size: 10553344 | Author: gy | Hits:

[VHDL-FPGA-Verilog] 8bitRISCCPU

Description: 8bit RISC cpu 设计资料包含夏宇闻老师的教程第8章-8bit RISC cpu design
Platform: | Size: 816128 | Author: dyfdown | Hits:

[Windows Develop] mipscpu-source

Description: mips cpu的实现.MIPS是世界上很流行的一种RISC处理器。MIPS公司的R系列就是在此基础上开发的RISC工业产品的微处理器。这些系列产品为很多计算机公司采用构成各种工作站和计算机系统。 -mips cpu implementation. MIPS is the world' s very popular as a RISC processor. MIPS company' s R series is based on the development of industrial products RISC microprocessor. These series of products for many computer companies used to create various workstations and computer systems.
Platform: | Size: 7025664 | Author: 汤龑鸣 | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 32位5级流水线CPU设计指令系统、指令格式、寻址方式、寄存器结构、数据表示方式、存储器系统、运算器、控制器和流水线结构等-32bit pipeline CPU
Platform: | Size: 187392 | Author: znl | Hits:

[Other] PipelineCPU

Description: Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
Platform: | Size: 847872 | Author: znl | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 5 stage pipeline CPU, verilog HDL code-5 stage pipeline CPU
Platform: | Size: 2048 | Author: dylan | Hits:

[VHDL-FPGA-Verilog] mips-cpu

Description: 单周期的mips处理器设计，用vhdl语言实现各个模块的功能-Single-cycle mips processor design, using vhdl language functions of each module
Platform: | Size: 117760 | Author: 王晓强 | Hits:

[VHDL-FPGA-Verilog] VHDL-for-Datapath

Description: MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd - memory buffer.vhd - buffer ALUcon.vhd - Alu controller pc.vhd - program counter REG - registers-MIPS CPU with Mulicycle Datapath. This is a custom RISC processor implemented to achieve the function of "lw, sw, add, sub, and, or, beq, j" Mem.vhd- memory buffer.vhd- buffer ALUcon.vhd- Alu controller pc.vhd- program counter REG- registers
Platform: | Size: 8192 | Author: zi | Hits:

[VHDL-FPGA-Verilog] vhdl-pipeline-mips0

Description: MIPS CPU WITH PIPELINE procesador MIPS-FZA -- Autor: mahdi ahmadi -- Email: mahdi@fza.ir -- mahdifza@yahoo.com -- -- Version: 1.0
Platform: | Size: 23552 | Author: mahdi | Hits:

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[ARM-PowerPC-ColdFire-MIPS] mips_creative

[MPI] source

[ARM-PowerPC-ColdFire-MIPS] or2000

[VHDL-FPGA-Verilog] CPU

[ARM-PowerPC-ColdFire-MIPS] mips3

[ARM-PowerPC-ColdFire-MIPS] MIPStest00

[Embeded-SCM Develop] IP_CORES

[VHDL-FPGA-Verilog] The_design_of_MIPS_CPU(VHDL)

[VHDL-FPGA-Verilog] mips1

[Other] cpu

[VHDL-FPGA-Verilog] 8bitRISCCPU

[Windows Develop] mipscpu-source

[Embeded-SCM Develop] mips

[VHDL-FPGA-Verilog] mips

[VHDL-FPGA-Verilog] CPU

[Other] PipelineCPU

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] mips-cpu

[VHDL-FPGA-Verilog] VHDL-for-Datapath

[VHDL-FPGA-Verilog] vhdl-pipeline-mips0

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