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Description: 已经在xilinx的ML555开发板上实现的PCIEx4的设计，其中带有DMA功能。满足pciexpress1.0规范。
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Size: 4633694 |
Author: 刘建中 |
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Description: 已经在xilinx的ML555开发板上实现的PCIEx4的设计，其中带有DMA功能。满足pciexpress1.0规范。-Already in the Xilinx ML555 development board to achieve PCIEx4 design, which features with DMA. Pciexpress1.0 meet the specification.
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Size: 4633600 |
Author: nuaa |
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Description: 赛灵思官方PCIE开发评估板ML555的硬件设计原理图。-Xilinx official the PCIE development evaluation board ML555 hardware design schematics.
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Size: 15236096 |
Author: zhucheng |
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Description: xilinx PCIE IP核 包括ddr2 memory interface
ML555开发板-xilinx PCIE IP cores
containing ddr2 memory interface
can be used on ML555 development kit
Platform: |
Size: 135168 |
Author: sun |
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Description: PCIE的DMA实现，在ML555开发板使用Verilog-PCIE' s DMA implementation using Verilog in the ML555 development board
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Size: 5999616 |
Author: 曹老三 |
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Description: 本文档介绍了一种基于Xilinx Endpoint Block Plus PCIe IP Core，由板卡主动发起的DMA设计。该设计利用通用的LocalLink 接口，所以方便的兼容支持Xilinx PCIe 硬核的器件，例如Virtex 5，Virtex 6，Spartan 6，并且实际在ML555 和ML605 开发板上实际测试通过。此外，驱动将板卡的控制封装起来，提供用户层简单的读写接口，方便上层程序的开发。-This document describes an approach based on Xilinx Endpoint Block Plus PCIe IP Core, initiated by the board of DMA Design. The design utilizes a common LocalLink interface, easy to support Xilinx PCIe hardcore compatible devices, such as Virtex 5, Virtex 6, Spartan 6, and actually ML555 ML605 development board and the actual test. In addition, the board of control of the driver package, and provides user-level read and write a simple interface to facilitate the development of the top programs.
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Size: 313344 |
Author: wu |
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