Search - modelsim

[VHDL-FPGA-Verilog] verilog4

Description: 用verilog语言编写的数码管显示实验程序。通过分频计数来使数码管以640ms间隔从1变化到F。压缩包内也包含此数码管显示实验程序的modelsim仿真文件。-Verilog language with digital display test program. By dividing the clock count to make the digital control to 640ms intervals from 1 to F. This package also contains a compressed digital display test program modelsim simulation files.
Platform: | Size: 78848 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] verilog5

Description: 用verilog语言编写的4位乘法器程序。通过循环移位进行4位二进制数的乘法运算。压缩包内也包含此4位乘法器程序的modelsim仿真文件。-Verilog language with 4-bit multiplier process. By cyclic shift for 4-bit binary number multiplication. This compressed package also contains four multipliers modelsim simulation program files.
Platform: | Size: 217088 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] verilog6

Description: 用verilog语言编写的VGA显示程序。通过本程序可以学习到VGA显示原理，及如何用verilog语言编写vga显示程序。压缩包内也包含此VGA显示程序的modelsim仿真文件。-Verilog language with the VGA display program. Through this program can learn to VGA Display principles, and how to use the verilog language vga display program. This package also contains compressed VGA display program modelsim simulation files.
Platform: | Size: 281600 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] Chapter-1

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 2048 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-2

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 5120 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-3

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 4096 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-4

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 7168 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-5

Description: Verilog数字系统设计教程(第2版)”这本书的思考题没有答案，要多做实验和仿真-• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 15360 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-6

Description: 练习六在verilog hdl中使用函数317 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 3072 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-7

Description: 练习七在verilog hdl中使用任务（task）319 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 7168 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] Chapter-8

Description: 练习八利用有限状态机进行时序逻辑的设计322 -• Source code of designs in chapters 1 to 8. • Chapter 8 designs include the SAYEH processor, its C Compiler, and its Sort program run files. • Several Designs, including SAYEH, that are programmed on Altera’s UP2 board are included in “Quartus UP2 Designs.zip” • The OVL directory has OVL library version 1.0 and its documentations • In the Software directory, the Altera directory contains Quartus II, related tools, and Altera device specifications. Please connect to www.altera.com and then click on “University Program” to obtain a license for Quartus II Web Edition. • In the Software directory, The MentorGraphics directory has the ModelSim-Altera simulation program. Please connect to www.altera.com and then click on “University Program” to obtain a license for ModelSim-Altera.
Platform: | Size: 335872 | Author: shixiaodong | Hits:

[VHDL-FPGA-Verilog] flash_simulate

Description: 在Modelsim环境下，Verilog语言编写的Flash模拟器。-In the Modelsim environment, Verilog simulator written in Flash.
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] p2s_code

Description: 并行输入，串行输出模块，输入的位宽在1--16位可变，包括测试平台，自己写的，绝对可用，已经通过modelsim仿真。-Parallel input, serial output module, the input bit-width of 1- 16-bit variable, including the test platform, write your own, absolutely free, Has passed the modelsim simulation.
Platform: | Size: 2048 | Author: 徐帅 | Hits:

[VHDL-FPGA-Verilog] Control

Description: 实现加法器的控制，利用verilog语言。在modelsim环境先实现。-Realization of adder control, the use of Verilog language. In the Modelsim environment to achieve.
Platform: | Size: 1024 | Author: ganlu1107 | Hits:

[VHDL-FPGA-Verilog] Behavioral-Modeling

Description: A Code that illustrates 12 bit switch, 2x1 Mux, 2x4 Decoder in behavioral modeling in Verilog HDL using modelsim IDE
Platform: | Size: 1024 | Author: Asad Abbas | Hits:

[VHDL-FPGA-Verilog] ADD_lab_manual_2K8

Description: This Advance Digital Design Manual, that is taught in our University, it takes from the basic to the advance in Verilog Programming using Modelsim IDE, very good for self learning-This is Advance Digital Design Manual, that is taught in our University, it takes from the basic to the advance in Verilog Programming using Modelsim IDE, very good for self learning
Platform: | Size: 621568 | Author: Asad Abbas | Hits:

[VHDL-FPGA-Verilog] EP3C8020111219125810_ROM_OK5

Description: 采用DSP builder v9.1实现正交两路单频输出，已经在EP3C80上面跑通，经实际验证是正确的。此例程非常简洁明了，可以作为DSP builder的入门示例。里面已经包含了生成好的modelsim仿真示例和仿真结果。-Achieved using DSP builder v9.1 orthogonal two single-frequency output, has been run through the EP3C80 above, are proven to be correct. This routine is very simple and clear, as DSP builder of the Getting Started Sample. Which has been included to generate good modelsim simulation Examples and simulation results.
Platform: | Size: 13917184 | Author: 刘洋 | Hits:

[VHDL-FPGA-Verilog] uart

Description: XILINX参考设计，uart，包括modelsim测试代码-XILINX reference design, uart, including modelsim test code
Platform: | Size: 29696 | Author: mend | Hits:

[VHDL-FPGA-Verilog] AssignmentP3

Description: Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx ISE and ModelSim simulator. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.
Platform: | Size: 141312 | Author: 魏攸 | Hits:

[VHDL-FPGA-Verilog] 61IC_S774

Description: sdram 仿真模型,用于verilog代码sdram行为级仿真-sdram modelsim model
Platform: | Size: 7168 | Author: wangzuo | Hits:

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