Search - modelsim 6.3

[Other resource] paobiao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。
Platform: | Size: 156342 | Author: 李华 | Hits:

[Books] modelsim使用教程

Description: 一本不错的介绍modemsim的电子书，希望能给大家带来些帮助-a good introductory modemsim of e-books, in hopes of giving us some more help
Platform: | Size: 342016 | Author: 周玲玲 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a
Platform: | Size: 155648 | Author: 李华 | Hits:

[Software Engineering] ModelsimUserGuide

Description: Modelsim使用教程，是SE5.3的版本的说明，有点老，不过同现在的6.2b相比，界面都差不多。-ModelSim Tutorial is SE5.3 version of that little old, but with 6.2b now compared to the interface are similar.
Platform: | Size: 505856 | Author: 张前 | Hits:

[VHDL-FPGA-Verilog] ModelSim_License

Description: Altera Modesim破解版的LICENCE. 下载解压后: 1.直接运行mentorkg.exe(生成的license.txt拷贝到D:\altera\80\modelsim_ae\下或者mentorkg.exe拷贝到此目录下运行). 2.设置环境变量lm_license_file="D:\altera\80\modelsim_ae\license.txt" 3.搞定-Altera Modesim cracked version of the LICENCE. Decompress after download: 1. Direct running mentorkg.exe (generated copy license.txt to the D: altera80modelsim_ae the next copy of this directory or mentorkg.exe run) .2. Lm_license_file = Set environment variables D: altera80modelsim_aelicense.txt 3. get
Platform: | Size: 313344 | Author: xingyu | Hits:

[OS program] vh2sc

Description: 将VHDL转换为C的软件将VHDL转换为C的软件-VH2SC is a free basic VHDL to SystemC converter. The converter handles a small subset of Synthesisable VHDL 87/93 language constructs. The current version translates all VHDL IEEE types to sc_int/sc_uint/integers and booleans this in order to maximise performance. The aim of the converter is to produce a cycle accurate model of synthesisable VHDL code. The converter runs on Windows Example1: Simple counter Convert the counter.vhd file to SystemC, c:VHDL2SystemCexample1>vh2sc-v-mti count.vhd VH2SC-> VHDL to SystemC Converter Ver 0.21** Alpha Release** (c)HT-Lab 2007 SQLite Version : 3.3.13 Parsing File : count.vhd Line 9** Info : library ieee ignored Line 28** Info : VH2SC Translation Disabled Line 32** Info : VH2SC Translation Re-Enabled Line 37** Info : process() translated to process_line37 Writing Header File : cnt.h Writing C++ File : cnt.cpp ** Info : Modelsim SC_MODULE_EXPORT(cnt) macro added The-v is a verbose flag and-mti is requi
Platform: | Size: 819200 | Author: whiz | Hits:

[VHDL-FPGA-Verilog] 16bitCLA

Description: 基于Verilog HDL的16位超前进位加法器分为3个功能子模块-Verilog HDL-based 16-bit CLA is divided into three functional sub-modules
Platform: | Size: 7168 | Author: 韩伟 | Hits:

[VHDL-FPGA-Verilog] modelsim_6.3f_6.4b_6.5_crck

Description: 目前这个生成的key在modelsim se 6.3f 6.4b 6.5测试没问题。因为这几个版本是我逐步升级的，应该说从6.3f~6.5的都可以用。测试环境为windows xp sp3. vista没有测试。按理说是一样的。使用过程中遇到的一些问题的解决办法关于key里面生成中文字符的情况产生原因是，windows当前用户名和主机名是中文，修改之后重新生成一次。在安装的时候要设置环境变量LM_LICENSE_FILE，指向lincense的的路径和文件名。需要在cmd下使用modelsim的命令，需要将modelsim的win32目录添加到环境变量path中，这些都是EDA软件安装的一些基本常识了。对于modelsim的较新版本，会有提示。但是还要设置LM_LICENSE_FILE。关于网卡号的设置可以使用-h的参数，更多参数请在命令行下使用-help来查看。 2009年9月14日测试支持最新的6.5C-modelsim se 6.3f 6.4b 6.5
Platform: | Size: 308224 | Author: yanghong | Hits:

[Other] synlify_ISE_ModlSim_postsimulation

Description: 我想很多人跟我一样，被ModelSim的后仿真搞的头晕脑胀。为了这个问题，我在网上找了很多的资料，但发现这些资料往往说的不明白。一些步骤被作者有意无意地省略掉，这常常给读者造成不必要的麻烦，所以我决定写下这一篇文章，把这3天我努力的结果拿出来，与大家分享-I think many people like me, the latter being ModelSim simulation out of Touyunnaozhang. To this question, I found a lot of online information, but found that such information is often said, do not understand. Of a number of steps are omitted intentionally or unintentionally, which often cause unnecessary trouble to the reader, so I decided to write this article, these three days out the results of my efforts to share with you
Platform: | Size: 857088 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] Verilog1C21B21A4_1237797332

Description: Verilog HDL Introduction 1.1 Verilog HDL Introduction 1.2 The basic concept of using the Verilog 1.3 Verilog HDL design concept of modular and hierarchical 1.4 Gate-level design module 1.5 data processing module design 1.6 Behavior Model 1.7 How to use the ModelSim-Verilog HDL Introduction 1.1 Verilog HDL Introduction 1.2 The basic concept of using the Verilog 1.3 Verilog HDL design concept of modular and hierarchical 1.4 Gate-level design module 1.5 data processing module design 1.6 Behavior Model 1.7 How to use the ModelSim
Platform: | Size: 4396032 | Author: vkiy | Hits:

[VHDL-FPGA-Verilog] 32Kfft

Description: 32KFFT例程，适用于Quartus II 5.0 or later。- This design example requires the following software package: o Quartus II 5.0 or later o FFT MegaCore v2.1.3 o ModelSim version 6.0 or later
Platform: | Size: 998400 | Author: J | Hits:

[VHDL-FPGA-Verilog] Crack_ModelSim_SE_6.3d

Description: Modsim6.3 Crack and license
Platform: | Size: 299008 | Author: bob chen | Hits:

[Embeded-SCM Develop] ModelSim.SE.6.6b.Keygen

Description: 1- Run MakeLic.bat file. 2- Copy licensefile.dat to a suitable place. 3- Define a user environment variable and name it LM_LICENSE_FILE . It must point to your license file. 4- Have fun )-1- Run MakeLic.bat file. 2- Copy licensefile.dat to a suitable place. 3- Define a user environment variable and name it LM_LICENSE_FILE . It must point to your license file. 4- Have fun )
Platform: | Size: 848896 | Author: artur | Hits:

[Software Engineering] Assignment-3

Description: Assignment 3 Construct VHDL models for 74-139 dual 2-to-4-line decoders using three description styles, i.e., behavioral, dataflow and structural descriptions. (1) Synthesize and (2) simulate these models respectively in the environment of Xilinx ISE and ModelSim simulator. When simulating these models, test vector(s) are required to stimulate the units under test (UUT). Reasonable test vectors are designed and created by your own as sources added to your VHDL project.-Assignment 3
Platform: | Size: 33792 | Author: 董振兴 | Hits:

[VHDL-FPGA-Verilog] 38-decoder

Description: 3-8译码器的Verilog硬件语言实现，开发环境是ModelSim-The 3-8 decoder Verilog hardware language development environment is ModelSim
Platform: | Size: 3072 | Author: klxl | Hits:

[VHDL-FPGA-Verilog] ex1

Description: 设计一个循环灯控制器，该控制器控制红、绿、黄三个发光管循环发亮。要求红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒。（假设外部提供频率为1MHz的方波信号）编程环境为Quartus II 11.0 仿真环境为 Modelsim 6.6d 通过仿真可以看出。系统复位后，红发光管亮2秒，绿发光管亮3秒，黄发光管亮1秒，三个发光管循环发亮。 -Design a loop lamp controller that controls the red, green and yellow three LED lights cycle. Requirements red LED light 2 seconds, the green LED light 3 seconds, yellow light-emitting tube light 1 second. (Assuming a frequency of 1MHz externally a square wave signal) Programming environment for Quartus II 11.0 Simulation environment for the Modelsim 6.6d The simulation can be seen. After a system reset, the red LED light 2 seconds, the green LED light 3 seconds, yellow light-emitting tube light 1 second, three LED lights cycle.
Platform: | Size: 438272 | Author: zhuang | Hits:

[VHDL-FPGA-Verilog] Example-b8-3

Description: 学习使用DO文件进行仿真的基本方法,根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程-DO learn how to use basic file simulation method, according to the syntax of the command or ModelSim provides Tcl/Tk language will flow simulation simulation Cmd command sequence written to the macro file extension "do" in, and then execute the file directly DO , you can complete the entire simulation process
Platform: | Size: 12288 | Author: 波罗的海 | Hits:

[VHDL-FPGA-Verilog] sequence-detector

Description: 3比特的任意二值序列检测器，Quartus 10.0+modelsim 6.5SE联仿真报告形式-3 bits of arbitrary binary sequence detector,simulation with Quartus 10.0+ modelsim 6.5SE，report forms
Platform: | Size: 90112 | Author: dailanfeng | Hits:

[Other] Example-b4-1

Description: 1.定制一个双端口RAM，DualPortRAM 2.在顶层工程中实例化这个RAM 3.实现这个工程，在Quartus II仿真器中做门级仿真在ModelSim中对这个工程进行RTL级仿真-1. Customize a dual-port RAM, DualPortRAM 2. In the top-level project instantiate RAM 3. To achieve this project, do gate-level simulator in Quartus II Simulation In this works in ModelSim RTL-level simulation
Platform: | Size: 319488 | Author: 朱潮勇 | Hits:

[Other] Example-b8-3

Description: 根据ModelSim提供的命令或者Tcl/Tk语言的语法，将仿真Cmd流程的仿真命令依次编写到扩展名为“do”的宏文件中，然后直接执行这个DO文件，就可以完成整个仿真流程 1.创建目录，学习DO文件 2.启动ModelSim，执行DO文件 3.执行仿真，观测波形-ModelSim command according to the syntax provided or Tcl/Tk language emulation process simulation Cmd command sequentially written to the macro file extension do , and then the DO file directly, you can complete the entire simulation process 1. Create a directory to learn DO file 2. Start ModelSim, DO file 3. Perform simulation waveform observation
Platform: | Size: 12288 | Author: 朱潮勇 | Hits:

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