Search - modelsim fir

[Other resource] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6507 | Author: zqh | Hits:

[Software Engineering] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228801 | Author: yaoming | Hits:

[Other] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合
Platform: | Size: 956 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] firmatlab

Description: fir在dspbuilder下产生VHDL源码及其测试激励文件时的matlab模型,在modelsim下仿真通过-fir in dspbuilder VHDL source code under test and document the incentive mat lab model, the simulation under through modelsim
Platform: | Size: 6144 | Author: zqh | Hits:

[VHDL-FPGA-Verilog] firfpga

Description: 在利用FPGA实现数字信号处理方面，分布式算法发挥着关键作用，与传统的乘积-积结构相比，具有并行处理的高效性特点。详细研究了基于FPGA、采用分布式算法实现FIR数字滤波器的原理和方法，并通过Xilinx ISE在Modelsim下进行了仿真。 -FPGA using digital signal processing, distributed algorithm plays a key role with the traditional product-plot structure compared with the efficient parallel processing features. Based on a detailed study of the FPGA, using distributed algorithm FIR digital filter method and the principle, and through the Xilinx ISE under the Modelsim simulation.
Platform: | Size: 228352 | Author: yaoming | Hits:

[VHDL-FPGA-Verilog] Fir

Description: 11 阶FIR 数字滤波器,verolog描述，通过modelsim 6.0 仿真，Quartue综合-11-order FIR digital filter, verolog description, modelsim 6.0 through simulation, Quartue integrated
Platform: | Size: 1024 | Author: shenyunfei | Hits:

[VHDL-FPGA-Verilog] FIR_Direkt_ak

Description: VHDL代码的直接型FIR滤波器22阶。Fa=48 kHz, Fc=10kHz 可以在ModelSim下仿真， FPGA实现。 -VHDL code of the direct-type 22-order FIR filter. Fa = 48 kHz, Fc = 10kHz can be under the ModelSim simulation, FPGA realization.
Platform: | Size: 1024 | Author: 李乔 | Hits:

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

Description: 文档中含有DDS的VHDL实现，FIR滤波器串并FPGA实现，synplify,ISE,ModelSim后仿真流程和FPGA设计的资料-document contains DDS implementation with VHDL , FIR filter serial to parallel and FPGA implementation, and synplify, ISE, ModelSim simulation and FPGA design
Platform: | Size: 1383424 | Author: francis davis | Hits:

[VHDL-FPGA-Verilog] FIR_filter

Description: Parallel FIR filter example. It is low-pass filter for CPLD or FPGA platforms. Project compiled and simulated in Modelsim
Platform: | Size: 237568 | Author: Serg | Hits:

[DSP program] fir-filter-in-Matlab-and-Modelsim

Description: 基于DSP Builder的fir滤波器，及在Modelsim上仿真工程文件，是在做基于FPGA的fir滤波器的一部分-The DSP Builder-based fir filter, and on the simulation project file in Modelsim is doing FPGA-based fir filter part of the
Platform: | Size: 10390528 | Author: pei | Hits:

[VHDL-FPGA-Verilog] fir_lowpass

Description: 硬件语言实现数字低通滤波器，使用ise11.1和modelsim se6.5 仿真测试-Hardware language digital low pass filter, the use of simulation testing ise11.1 and modelsim se6.5
Platform: | Size: 545792 | Author: linzi | Hits:

[VHDL-FPGA-Verilog] fir

Description: 用Verilog语言设计的一个数字FIR低通滤波器，很实用，通过modelsim仿真成功-Verilog language to design a digital FIR low-pass filter, very practical, through modelsim simulation success
Platform: | Size: 1685504 | Author: liu | Hits:

[VHDL-FPGA-Verilog] my_fir

Description: Verilog 写的FIR滤波器，modelsim仿真通过-Verilog write FIR filter, modelsim simulation through
Platform: | Size: 1024 | Author: 韩帅 | Hits:

[Other] da_fir

Description: 基于FPGA分布式算法FIR滤波器verilog代码（本人小论文代码，通过验证）本文提出一种新的FIR滤波器FPGA实现方法。讨论了分布式算法原理，并提出了基于分布式算法FIR滤波器的实现方法。通过改进型分布式算法结构减少硬件资源消耗，用流水线技术提高运算速度，采用分割查找表方法减小存储规模，并在Matlab和Modelsim仿真平台得到验证。为了节省FPGA逻辑资源、提高系统速度，设计中引入了分布式算法实现有限脉冲响应滤波器(Finite Impulse Response, FIR)。由于FIR滤波器在实现上主要是完成乘累加MAC的功能，采用传统MAC算法设计FIR滤波器将消耗大量硬件资源。而采用分布式算法 (Distributed Arithmetic, DA)，将MAC运算转化为查找表(Look-Up-Table, LUT)输出，不仅能在硬件规模上得到改善，而且更易通过实现流水线设计来提高速度。因此本文采用分布式算法设计一个可配置的FIR滤波器，并以31阶的低通FIR滤波器为例说明分布式算法滤波器结构。- FPGA verilog
Platform: | Size: 6144 | Author: 石康 | Hits:

[VHDL-FPGA-Verilog] myfir

Description: VHDL设计的FIR滤波器，有Matlab设计文件，Quartus II工程以及Modelsim仿真结果和说明文件-VHDL design FIR filters, Matlab design documents, Quartus II project and Modelsim simulation results and documentation
Platform: | Size: 2861056 | Author: fangying | Hits:

[VHDL-FPGA-Verilog] fir_verilog_matlab

Description: 本设计是基于FPGA的一个FIR低通滤波器设计，要求使用Verilog语言编写滤波器模块，通过编译和综合，并通过Matlab和modelsim联合仿真验证设计结果。-This design is a FIR low-pass filter design based on FPGA, use Verilog to program filter module, and joint simulation by Matlab and modelsim to validate the design results.
Platform: | Size: 1352704 | Author: 郭婷 | Hits:

[VHDL-FPGA-Verilog] fir

Description: 使用VHAL语言编写的一个fir滤波器，通过modelsim进行仿真-fir filter
Platform: | Size: 8890368 | Author: 舒占军 | Hits:

[Other] fir

Description: MATLAB设计fir数字滤波器，结合modelsim软件仿真。(MATLAB design FIR digital filter)
Platform: | Size: 940032 | Author: 眼前人 | Hits:

[VHDL-FPGA-Verilog] fir4tap using array

Description: 4 tap fir filter using by passing multiplier
Platform: | Size: 11264 | Author: divya_r | Hits:

Category

Source Code

Web/Internet

Develop Tools

Document

Other

Search in results

OS

Platform

Language

File Type

Search list

[Other resource] firmatlab

[Software Engineering] firfpga

[Other] Fir

[VHDL-FPGA-Verilog] firmatlab

[VHDL-FPGA-Verilog] firfpga

[VHDL-FPGA-Verilog] Fir

[VHDL-FPGA-Verilog] FIR_Direkt_ak

[VHDL-FPGA-Verilog] FPGAdesignandFIRimplementation

[VHDL-FPGA-Verilog] FIR_filter

[DSP program] fir-filter-in-Matlab-and-Modelsim

[VHDL-FPGA-Verilog] fir_lowpass

[VHDL-FPGA-Verilog] fir

[VHDL-FPGA-Verilog] my_fir

[Other] da_fir

[VHDL-FPGA-Verilog] myfir

[VHDL-FPGA-Verilog] fir_verilog_matlab

[VHDL-FPGA-Verilog] fir

[Other] fir

[VHDL-FPGA-Verilog] fir4tap using array

CodeBus www.codebus.net