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Description: modelsim+dc开发的4级流水线结构的MIPS CPU,完成基本的逻辑运算和跳转。测试程序为希尔排序,结果正确。
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Size: 307462 |
Author: 杨春 |
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Description: modelsim+dc开发的4级流水线结构的MIPS CPU,完成基本的逻辑运算和跳转。测试程序为希尔排序,结果正确。-modelsim+ dc development of four pipelined structure MIPS CPU, the completion of the basic logic operations and Jump. Test procedure for the Hill to sort the results correctly.
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Size: 307200 |
Author: 杨春 |
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Description: ModelSim下用SystemC做设计验证方法与示例-ModelSim using SystemC to do design verification methods and sample
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Size: 1139712 |
Author: 邹积银 |
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Description: 一个微处理器的Verilog代码,根据英文书籍《数字设计与架构》中的例子而写,能够运行MIPS指令,能正确执行跳转指令。通过modelsim仿真,含测试代码。-Verilog code for a microprocessor, according to the English book " Digital Design and Architecture" was written in the example, to run MIPS instructions to jump correctly. By modelsim simulation, with test code.
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Size: 208896 |
Author: 楚寒 |
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Description: Modelsim+DC开发的4级流水线结构的MIPS CPU-mips 4level cpu
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Size: 307200 |
Author: 秦琴 |
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Description: 使用verilog代码描述了一种简单的单周期MIPS处理器实现,并在ModelSim SE6.5c调试通过。-The verilog code describes a simple, single-cycle MIPS processor implementation, and debugging through in ModelSim SE6.5c,.
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Size: 134144 |
Author: 赵成龙 |
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Description: 是用verilog写的带uart的简单controller,使用的是mips指令,用modelsim仿真,波形正确-With uart verilog write a simple controller, use the mips instruction the modelsim simulation, waveform correctly
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Size: 72704 |
Author: 张三 |
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Description: 在Modelsim中实现类MIPS多周期流水化处理器-In Modelsim achieve class multi-cycle pipelined processor MIPS
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Size: 456704 |
Author: Wing |
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Description: 运用verilog语言实现的MIPS指令集,包括加、减、比较、与、异或等指令。运用五级流水线,设置IF,ID,EX,MEM、WB五个栈间计算模块。运用了forwarding和stop技术。可以使用modelsim验证。
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Size: 141565 |
Author: cjc87267137 |
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Description: 这是verilog实现的MIPS多周期CPU在modelsim下面仿真通过-This is achieved verilog CPU MIPS multi-cycle simulation in modelsim below by
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Size: 169984 |
Author: zhql945 |
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