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[Other resource] ModelSim_TestBench_VHDL

Description: ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
Platform: | Size: 1468 | Author: 汤维 | Hits:

[VHDL-FPGA-Verilog] shift_register_testbench

Description: 16位的移位寄存器，加上testbench,可以在modelsim里面运行~-16 of the shift register and testbench, modelsim the inside running ~
Platform: | Size: 23552 | Author: yeqing | Hits:

[VHDL-FPGA-Verilog] hdb3_verilog

Description: modelsim工程，用verilog实现的HDB3编码，以及测试程序testbench-modelsim works with verilog realized HDB3 coding, and testing procedures testbench
Platform: | Size: 22528 | Author: chengroc | Hits:

[VHDL-FPGA-Verilog] ModelSim_TestBench_VHDL

Description: ModelSim TestBench的VHDL模版-ModelSim VHDL template TestBench
Platform: | Size: 1024 | Author: 汤维 | Hits:

[VHDL-FPGA-Verilog] RISCMCU

Description: riscMCU的VHDL实现，内附有modelsim仿真testbench和文档说明-riscMCU VHDL, modelsim containing a simulation testbench and documentation shows
Platform: | Size: 594944 | Author: wutailiang | Hits:

[VHDL-FPGA-Verilog] PWM

Description: 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench-Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench
Platform: | Size: 348160 | Author: horse | Hits:

[source in ebook] XiaYuWen_8_RISC_CPU

Description: 夏宇闻8位RISC_CPU的完整代码+TESTBENCH（已调试） modelsim工程文件，包括书中所测试的三个程序和相关数据，绝对可用~所有信号名均遵从原书。在论坛中没有找到testbench的，只有一个mcu的代码，但很多和书中的是不一样的，自己改了下下~`````大家多多支持啊~`我觉得书中也还是有些不尽如人意的地方，如clk_gen.v中clk2,clk4是没有用的，assign clk1=~clk再用clk1的negedge clk1来触发各个module也是不太好的，会使时序恶化，综合时很可能会setup vio的，所以觉得直接用clk的上升沿来触发各个module比较好-XIA Yu-Wen 8 RISC_CPU complete code+ TESTBENCH (has debug) modelsim project documents, including the book by the three test procedures and related data, the absolute available ~ all signals were found in compliance with the original name. Not found in the forums Testbench, and there is only one mcu code, but many and the book is not the same as he changed a lot of support under the U.S. ~````` ah ~ `I think the book is still some uncertainty unsatisfactory places, such as clk_gen.v in clk2, clk4 is of no use, assign clk1 = ~ clk reuse CLK1 of negedge clk1 to trigger module is not all good, cause the deterioration of timing, synthesis is likely to setup vio, therefore, feel that the direct use of the rising edge of clk to trigger each module is better
Platform: | Size: 86016 | Author: 刘志伟 | Hits:

[VHDL-FPGA-Verilog] hssdrc_latest.tar

Description: HSSDRC IP core is the configurable universal SDRAM controller with adaptive bank control and adaptive command pipeline. HSSDRC IP core and IP core testbench has been written on SystemVerilog and has been tested in Modelsim. HSSDRC IP core is licensed under MIT License
Platform: | Size: 424960 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] generic_testbench

Description: VHDL中关于generic的用法，及其testbench，可以使用Modelsim仿真查看其功能-the usage of generic,a testbench file is given, we can use it to simulate the generic s function
Platform: | Size: 2048 | Author: xietianjiao | Hits:

[VHDL-FPGA-Verilog] vhdltestbench

Description: testbench,VHDL的，适合初学者使用-testbench
Platform: | Size: 321536 | Author: liushuai | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 异步fifo，用Verilog编写，包含testbench，已经通过modelsim调试，内含文档和波形图-Asynchronous fifo, to prepare to use Verilog, including testbench, debug modelsim has passed, including documents and wave
Platform: | Size: 40960 | Author: iechshy1985 | Hits:

[VHDL-FPGA-Verilog] Modelsim_fredevider_testbench_TEXTIO

Description: 此文档通过分频器的例子描述了如何使用modelsim，如何编写testbench以及textio的使用-This document is an example through the divider describes how to use the modelsim, how to write a testbench and use textio
Platform: | Size: 256000 | Author: 二米阳光 | Hits:

[VHDL-FPGA-Verilog] TestBench

Description: 怎样写testbench 本文的实际编程环境：ISE 6.2i.03 ModelSim 5.8 SE Synplify Pro 7.6 编程语言 VHDL 在ISE 中调用ModelSim 进行仿真-、assert (s_cyi((DWIDTH-1)/4) = 0 ) and (s_ovi = 0 ) and (s_qutnt = conv_std_logic_vector(v_quot,DWIDTH)) and (s_rmndr = conv_std_logic_vector(v_remd,DWIDTH)) report "ERROR in division!" severity failure
Platform: | Size: 90112 | Author: lei | Hits:

[Other] cpu86model

Description: This is intel 8088 x86 IP core, contain software complier & modelsim testbench
Platform: | Size: 199680 | Author: taylor.xu | Hits:

[VHDL-FPGA-Verilog] ModelSimweisijiaocheng

Description: modelsim 使用流程，一个记数仿真器详细设计步骤， FORCE和RUN两个命令解释，TestBench的一个例子。-modelsim using the process, a detailed design of the emulator counting steps, FORCE, and RUN 2 command interpreter, TestBench an example.
Platform: | Size: 2037760 | Author: cq | Hits:

[VHDL-FPGA-Verilog] Desktop

Description: 四选一多路选择器 modelsim testbench-Select more than one four-way selector modelsim testbench
Platform: | Size: 95232 | Author: 耿 | Hits:

[Windows Develop] testbench

Description: vhdl modelsim testbench examples-vhdl modelsim testbench for modelsim with vhdl examples
Platform: | Size: 2048 | Author: nono | Hits:

[Other] 61i_atan_cordic_v2_0_vhdl_ise

Description: my_atan_cordic.xco - Core parameter file my_atan_cordic.vho - Core VHDL instantiation template my_atan_cordic.vhd - Core VHDL simulation file (only for simulation) my_atan_cordic.edn - Core EIDF netlist (only for implementation) x_in_cos.dat - input data for the simulation (only for simulation) y_in_cos.dat - input data for the simulation (only for simulation) cordic_functional.do - ModelSim do file for functional simulation cordic_timing.do - ModelSim do file for timing simulation design_top.ucf - contrsaints file (only for implementation) design_top.vhd - VHDL toplevel design_top_tb.vhd - VHDL testbench
Platform: | Size: 118784 | Author: d | Hits:

[VHDL-FPGA-Verilog] VHDL--testbench

Description: VHDL 的testbench 编写风格及技巧，有助利用modelsim做仿真，一看就会！-The testbench VHDL writing style and skills will help make using modelsim simulation, a look will be!
Platform: | Size: 227328 | Author: 陈华 | Hits:

[Embeded-SCM Develop] ModelSim电子系统分析及仿真

Description: 此文档详细说明了如何利用Modelsim软件对FPGA逻辑代码进行功能仿真和时序仿真的方法，并通过相关例子进行讲解说明(This document explains in detail how to use Modelsim software to perform functional simulation and time series simulation of FPGA logic code, and explain how to use some examples.)
Platform: | Size: 48652288 | Author: ZSMCDUT | Hits:
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