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[VHDL-FPGA-Verilog] uart2fli

Description: Modelsim FLI接口设计实例，适合学习Modelsim fli接口编程者学习。-Modelsim FLI interface design for learning Modelsim fli learn programming interface.
Platform: | Size: 92160 | Author: xxx | Hits:

[VHDL-FPGA-Verilog] S8_VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中 4。具体设计参考代码。-1. Source file stored in the src directory, QII stored in the project file directory Proj 2. Program' s function is displayed on the monitor in the VGA color stripes, a total of eight kinds of colors, you can use the embedded logic analyzer observation signal 3. modelsim simulation document proj- simulation- modelsim 4. Specific reference code.
Platform: | Size: 628736 | Author: 刘飞 | Hits:

[VHDL-FPGA-Verilog] VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中 4。具体设计参考代码。-1. The source file in src directory, QII project file saved in Proj directory 2. Program implementation function is to display color VGA display stripes, a total of eight kinds of colors, you can use the embedded logic analyzer observation signal 3. modelsim simulation file in proj- simulation- modelsim of 4. The specific design reference to the code.
Platform: | Size: 4168704 | Author: jiehao | Hits:

[VHDL-FPGA-Verilog] S6_VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中 4。具体设计参考代码。 -1. Source file in src directory, QII Proj project files in the directory 2. Program implementation function is displayed on the VGA display colored stripes, a total of 8 colors, you can use the embedded logic analyzer observation signal 3. modelsim simulation file in proj- simulation- modelsim in 4. Specific design reference code.
Platform: | Size: 232448 | Author: 陈亮 | Hits:

[VHDL-FPGA-Verilog] S8_VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中 4。具体设计参考代码。 -1. Source file in src directory, QII Proj project files in the directory 2. Program implementation function is displayed on the VGA display colored stripes, a total of 8 colors, you can use the embedded logic analyzer observation signal 3. modelsim simulation file in proj- simulation- modelsim in 4. Specific design reference code.
Platform: | Size: 230400 | Author: 袁方 | Hits:

[VHDL-FPGA-Verilog] S6_VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中 4。具体设计参考代码。-1. Save the source file in the src directory, QII project files in the directory Proj 2. Program to achieve the function of the VGA monitor display color stripes, a total of eight colors, you can use the embedded logic analyzer observation signal 3. modelsim simulation file in proj- simulation- modelsim, 4. Specific design reference code.
Platform: | Size: 4129792 | Author: 成语 | Hits:

[VHDL-FPGA-Verilog] verilog6

Description: 用verilog语言编写的VGA显示程序。通过本程序可以学习到VGA显示原理，及如何用verilog语言编写vga显示程序。压缩包内也包含此VGA显示程序的modelsim仿真文件。-Verilog language with the VGA display program. Through this program can learn to VGA Display principles, and how to use the verilog language vga display program. This package also contains compressed VGA display program modelsim simulation files.
Platform: | Size: 281600 | Author: 广子 | Hits:

[VHDL-FPGA-Verilog] S6_VGA

Description: 1。源文件保存在src目录，QII的工程文件保存在Proj目录； 2。程序实现的功能是在VGA显示器上显示彩色条纹，共8种颜色， 可以使用嵌入式逻辑分析仪观测信号； 3。modelsim仿真文件在proj--simulation--modelsim中-1. The source file is saved in the src directory QII project file is saved in the directory Proj 2. The functionality of the program is displayed on a VGA monitor color stripes, 8 colors, you can use the embedded logic analyzer observed signals 3. the modelsim simulation files in the proj- simulation- modelsim
Platform: | Size: 3196928 | Author: 丁俊辉 | Hits:

[VHDL-FPGA-Verilog] sobel

Description: 由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
Platform: | Size: 10222592 | Author: 丶大娱乐家 | Hits:

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