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[VHDL-FPGA-Verilog] 16位快速乘法器

Description: VHDL语言实现的16位快速乘法器-VHDL of 16 rapid Multiplier
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] multi_vhdl

Description: 四位乘法器的VHDL源程序-four Multiplier VHDL source
Platform: | Size: 1024 | Author: 张庆辉 | Hits:

[VHDL-FPGA-Verilog] 嵌入式系统试验报告-乘法器-VHDL语言

Description: 嵌入式系统的乘法器试验报告 包括源代码 用VHDl语言编写-Embedded System multiplier test report including source code language used VHDl
Platform: | Size: 9216 | Author: 康抗 | Hits:

[VHDL-FPGA-Verilog] Booth_Multiplier

Description: 布斯乘法器的VHDL程序,下載後直接解壓縮複製貼上到你的EDATOOL就可以.-Booth multiplier VHDL procedures downloaded directly extract copy affixed to the EDATOOL you can.
Platform: | Size: 1024 | Author: 韓堇 | Hits:

[VHDL-FPGA-Verilog] BoothMultiplier

Description: -- Booth Multiplier -- This file contains all the entity-architectures for a complete -- k-bit x k-bit Booth multiplier. -- the design makes use of the new shift operators available in the VHDL-93 std -- this design passes the Synplify synthesis check -- download from: www.fpga.com.cn & www.pld.com.cn--- Booth Multiplier-- This file contains a ll the entity-architectures for a complete-- k- bit x k-bit Booth multiplier.-- the design mak es use of the new shift operators available in th e VHDL-93 std-- this design passes the Synplify synthesis check-- download from : www.fpga.com.cn
Platform: | Size: 2048 | Author: 罗兰 | Hits:

[Other] DesignofVeryDeepPipelinedMultipliersforFPGAs(IEEE)

Description: 关于FPGA流水线设计的论文 This work investigates the use of very deep pipelines for implementing circuits in FPGAs, where each pipeline stage is limited to a single FPGA logic element (LE). The architecture and VHDL design of a parameterized integer array multiplier is presented and also an IEEE 754 compliant 32-bit floating-point multiplier. We show how to write VHDL cells that implement such approach, and how the array multiplier architecture was adapted. Synthesis and simulation were performed for Altera Apex20KE devices, although the VHDL code should be portable to other devices. For this family, a 16 bit integer multiplier achieves a frequency of 266MHz, while the floating point unit reaches 235MHz, performing 235 MFLOPS in an FPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and other considerations to apply the technique in real designs are also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
Platform: | Size: 179200 | Author: 李中伟 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 交通灯程序《数字电路EDA入门－VHDL程序实例》---交通灯程序例子,,C-C++ -Traffic lights procedure digital circuit EDA entry-VHDL instances procedure--- example traffic lights,, C-C++
Platform: | Size: 3072 | Author: | Hits:

[VHDL-FPGA-Verilog] cf_fp_mul

Description: 浮点型的乘法器,采用VHDL语言描述浮点型的乘法器,文中包含测试文件-Floating-point type multiplier using VHDL language to describe the type floating-point multiplier, the text included in the test document
Platform: | Size: 687104 | Author: asdtgg | Hits:

[VHDL-FPGA-Verilog] mutip

Description: 16位乘法器 16位乘法器 -16-bit multiplier 16 multiplier 16 multiplier
Platform: | Size: 1024 | Author: | Hits:

[VHDL-FPGA-Verilog] test

Description: VHDL实现倍频--偶数倍 分频电路 --分频倍数=2（n+1）-VHDL realize many times frequency multiplier circuit dual frequency multiplier = 2 (n+ 1)
Platform: | Size: 145408 | Author: 杨守望 | Hits:

[DSP program] MulPar

Description: 八位乘法器VHDL语言实现。使用的工具的ISE7.1，实现八乘八的位相乘。-8 Multiplier VHDL language. Tools used ISE7.1, realize eight by eight-bit multiplication.
Platform: | Size: 2048 | Author: 周东永 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 用VHDL语言编写的一个乘法器校程序 是基于BOOTH算法的 -VHDL language using a multiplier BOOTH school program is based on the algorithm
Platform: | Size: 1024 | Author: 杨天 | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: booth乘法器： 16*16有符号乘法器，Booth编码，简单阵列，Ripple Carry Adder-booth multiplier:
Platform: | Size: 3072 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] systolic

Description: 脉动乘法器：一个GF(2m)域上的Digit-Serial 脉动结构（Systolic）的乘法器-Pulse Multiplier: a GF (2m) domain on the Digit-Serial pulsation structure (Systolic) the multiplier
Platform: | Size: 2560000 | Author: chenyi | Hits:

[VHDL-FPGA-Verilog] multiply

Description: 好用的浮点乘法器，可完成32位IEEE格式的浮点乘法，经过仿真通过-Easy to use floating-point multiplier, to be completed by 32-bit IEEE format floating-point multiplication, through simulation through
Platform: | Size: 1024 | Author: gulu | Hits:

[VHDL-FPGA-Verilog] multi8x8

Description: 实现了VHDL乘法器，8位乘法操作的完成-VHDL realize a multiplier, an 8-bit multiplication operation completed
Platform: | Size: 3072 | Author: zxzx | Hits:

[VHDL-FPGA-Verilog] Multiplier

Description: 用VHDL语言描述的几个乘法器实例，如串行阵列乘法器等-VHDL language used to describe a few examples of multipliers, such as array multipliers, such as serial
Platform: | Size: 279552 | Author: liuning | Hits:

[VHDL-FPGA-Verilog] multiplier

Description: 该乘法器是由8位加法器构成的以时序方式设计的8位乘法器。 其乘法原理是：乘法通过逐项移位相加原理来实现，从被乘数的最低位开始，若为1，则乘数左移后与上一次的和相加；若为0，左移后以全零相加，直至被乘数的最高位。-The multiplier is 8-bit adder consisting of time-series design to the 8-bit multiplier. The multiplication principle is: the sum of multiplication through the principle of each shift to achieve, from the beginning of the lowest multiplicand, if 1, then left after the multiplier and the sum of the last if for 0, left after zero-sum in full, until the highest bit multiplicand.
Platform: | Size: 103424 | Author: lsp | Hits:

[VHDL-FPGA-Verilog] 67719585-Booth-Multiplier-Vhdl-Code

Description: vhdl code for booth multiplier-vhdl code for booth multiplier...........................
Platform: | Size: 10240 | Author: satya | Hits:

[Communication-Mobile] Booth-Multiplier-VHDL-Code

Description: 布斯乘法器 Booth Multiplier VHDL Code-Booth Multiplier VHDL Code
Platform: | Size: 5120 | Author: li | Hits:
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