Location:
Search - nand o
Search list
Description: 由三星的2442修改而来,正确引导eboot,请注意用三星公版的硬件配置,具体可以参考QQ2440,因为我在些平台上跑过,具体操作
1.target settings : post-linker:选择为 ARM fromELF
2.ARM assembler与 ARM c Compiler 的 architecture or processor 选择为:ARM920T
3.ARM linker的 output:RO base为 0x00000000 (当仿真时为:0x30000000),layout的 object/sysmbol:为2440init.o
section:Init
4.ARM fromELF 的 output:format:plain binary , output file name:nboot.bin
下面为全部源码,注意用ADS编译
2442addr.h
2442addr.inc
2442init.s
2442lib.c
2442lib.h
2442loader-1208.c
2442slib.h
2442slib.s
Def.h
k9s1208_s.s
Memcfg.inc
Nand.h
Nand_mini.c
Option.h
Option.inc
Platform: |
Size: 1195715 |
Author: lzy |
Hits:
Description: 由三星的2442修改而来,正确引导eboot,请注意用三星公版的硬件配置,具体可以参考QQ2440,因为我在些平台上跑过,具体操作
1.target settings : post-linker:选择为 ARM fromELF
2.ARM assembler与 ARM c Compiler 的 architecture or processor 选择为:ARM920T
3.ARM linker的 output:RO base为 0x00000000 (当仿真时为:0x30000000),layout的 object/sysmbol:为2440init.o
section:Init
4.ARM fromELF 的 output:format:plain binary , output file name:nboot.bin
下面为全部源码,注意用ADS编译
2442addr.h
2442addr.inc
2442init.s
2442lib.c
2442lib.h
2442loader-1208.c
2442slib.h
2442slib.s
Def.h
k9s1208_s.s
Memcfg.inc
Nand.h
Nand_mini.c
Option.h
Option.inc-By Samsung from 2442 to amend, correct guidance eboot, Please note that Samsung used the public version of the hardware configuration, can refer to specific QQ2440, because I ran in some platforms, the specific operation 1.target settings: post-linker: choice for the ARM fromELF2.ARM assembler and ARM c Compiler of the architecture or processor choices: ARM920T3.ARM linker
Platform: |
Size: 1195008 |
Author: lzy |
Hits:
Description: Linux 2.6.13之后,NAND Flash的oob使用方法已经改变了;yaffs文件系统也因此改变。但是它的映象制作工具mkyaffsimage没有改过来。这是已经修改过的。-Linux 2.6.13 after, NAND Flash to use the OOB has changed yaffs file system also changed. But it
Platform: |
Size: 288768 |
Author: 韦东 |
Hits:
Description: sbc2410 移植u-boot 1.3.4 的修改部分
需要在borad/sbc2410x/Makefile 下添加编译nand.o
-sbc2410 transplant u-boot 1.3.4 changes borad/sbc2410x/Makefile part of the need to add compiler nand.o
Platform: |
Size: 8192 |
Author: 曹某某 |
Hits:
Description: verilog的简要教程
基本逻辑门,例如a n d、o r和n a n d等都内置在语言中。
• 用户定义原语( U D P)创建的灵活性。用户定义的原语既可以是组合逻辑原语,也可以
是时序逻辑原语。
• 开关级基本结构模型,例如p m o s 和n m o s等也被内置在语言中。-Verilog tutorial briefly the basic logic gates, such as and, or and NAND are built in the language. • user-defined primitives (UDP) to create flexibility. User-defined primitives are the combinational logic can be the original language may also be a temporal logic primitives. • The basic structure of switch-level models, such as PMOS and NMOS are also being built in the language.
Platform: |
Size: 4169728 |
Author: 阿春 |
Hits:
Description: This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to
provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller
solution in small die size. To reduce total system cost, the S3C2410X includes the following
components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management,
LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM
Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen
Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface,
2-ch SPI and PLL for clock generation.
Platform: |
Size: 2018304 |
Author: Quang Truong |
Hits:
Description: Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate VCCQ for 5 volt I/O tolerance
n Automated Program and Erase
— Page program: 512 + 16 bytes
— Block erase: 8 K + 256 bytes
n Block architecture
— 8 Kbyte blocks + 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page + 16 byte spare area for ECC and other
system overhead information
n Fast read and program performance (typical values)
— Read: < 7 μs initial, < 50 ns sequential
— Program: 200 μs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
n Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability-Single power supply operation
— Full voltage range: 2.7 to 3.6 volt read, erase, and
program operations
— Separate VCCQ for 5 volt I/O tolerance
n Automated Program and Erase
— Page program: 512+ 16 bytes
— Block erase: 8 K+ 256 bytes
n Block architecture
— 8 Kbyte blocks+ 256 byte spare area
(separately erasable, readable, and programmable)
— 512 byte page+ 16 byte spare area for ECC and other
system overhead information
n Fast read and program performance (typical values)
— Read: < 7 μs initial, < 50 ns sequential
— Program: 200 μs (full page program at 400 ns/byte)
— Erase: < 2 ms/8 Kbyte block
n Pinout and package
— Industry Standard NAND compatible pinout with 8-bit
I/O bus and control signals
— TSOP-II 44/40 pin package (standard and reverse)
with copper lead frame for higher reliability
— 40-ball FBGA package provides higher reliability
Platform: |
Size: 847872 |
Author: enyou |
Hits:
Description: Direct (w/o ram usage) jtag nand flash programmer for several Qualcomm CPUs. Uses JLink
Platform: |
Size: 15360 |
Author: flowswitch |
Hits:
Description: 用VHDL实现NAND Flash 的I/O 读写操作-with VHDL programme realize NAND Flash I/O read & write
Platform: |
Size: 19456 |
Author: wuqixuan |
Hits:
Description: sdio 说明DIO在SD标准上定义了一种外设接口。目前,SDIO有两类主要应用——可移动和不可移动。目前的可移动设备作为Palm和Windows Mobile的扩展设备,用来增加蓝牙、照相机、GPS和802.11b功能。不可移动设备遵循相同的电气标准,但不要求符合物理标准。某些手机内包含通过SDIO连接CPU的802.11芯片。此举将“珍贵”的I/ O管脚资源用于更重要的功能。
-sdio instructions on DIO in the SD standard defines a peripheral interface. Currently, SDIO There are two main applications- movable and immovable. The current mobile devices as Palm and Windows Mobile expansion devices to add Bluetooth, camera, GPS and 802.11b capabilities. Mobile devices can not follow the same electrical standards, but does not meet the physical standards required. Contains some phones to connect the CPU via SDIO 802.11 chip. This will " precious" the I/O pin resources for more important functions.
Platform: |
Size: 81920 |
Author: ye |
Hits:
Description: SMDK2413 (Samsung MCU Development Kit) for S3C2413X is a platform that is suitable for code development of SAMSUNG s S3C2413X 16/32-bit RISC microcontroller (ARM926EJ-S) for hand-held devices and general applications. The S3C2413X consists of 16-/32-bit RISC (ARM926EJ-S) CPU core, separate 8KB instruction and 8KB data cache, MMU to handle virtual memory management, LCD controller (STN & TFT), NAND flash boot loader, System Manager (chip select logic and SDRAM controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O ports, RTC, 8-ch 10-bit ADC and touch screen interface, IIC-BUS interface, IIS-BUS interface, USB host, USB device, SD host & multimedia card interface, ATA Interface, IrDA, Camera Interface, Watch Dog Timer, 2-ch SPI and PLL for clock generation. The SMDK2413 consists of S3C2413X, boot EEPROM (flash ROM), SDRAM, LCD interface, two serial communication ports, configuration switches, JTAG interface and status LEDs.
Platform: |
Size: 2135040 |
Author: fateme |
Hits:
Description: 本源码是基于S3C—6430的ARM11嵌入式开发板的NAND FLASH程序的编写。NAND写回速度快、芯片面积小,特别是大容量使其优势明显。页是NAND中的基本存贮单元,一页一般为512 B(也有2 kB每页的large page NAND FLASH),多个页面组成块。不同存储器内的块内页面数不尽相同,通常以16页或32页比较常见。块容量计算公式比较简单,就是页面容量与块内页面数的乘积。根据FLASH Memory容量大小,不同存储器中的块、页大小可能不同,块内页面数也不同。例如:8 MB存储器,页大小常为512 B、块大小为8 kB,块内页面数为16。而2 MB的存储器的页大小为256 B、块大小为4 kB,块内页面数也是16。NAND存储器由多个块串行排列组成。实际上,NAND型的FLASHMemory可认为是顺序读取的设备,他仅用8 b的I/O端口就可以存取按页为单位的数据。NAND在读和擦写文件、特别是连续的大文件时,速度相当快。-NAND write-back speed, small chip area, especially the large capacity make it obvious advantages. Page in the NAND storage unit, a general 512 B, (also have 2 kB per page large page NAND FLASH), multiple page composition. Number of pages within the memory block is different, usually more common 16 or 32. Block capacity formula is relatively simple, is the product of the page capacity and number of pages in the block. FLASH Memory size memory block, the page size may be different, the number of pages in the block. For example: 8 MB of memory, the page size is often 512 B, the block size of 8 kB, the number of pages in the block 16. The page size of 2 MB of memory, 256 B, the block size is 4 kB block, number of pages is 16. NAND memory by more than one block of the serial arrangement. In fact, NAND FLASHMemory can be considered to be the order of read devices, he took only 8-b I/O ports can access the data by page. NAND read and erase files, especially consecutive large files very fast.
Platform: |
Size: 3072 |
Author: wangan |
Hits:
Description: k9f28xxu0c中文数据手册
16M 8 位8M 16 位NAND Flash 存储器K9F28XXU0C
概述
K9F28XXU0C 是一个含有4M 位备用容量的128M 位Flash 存储器提供16M 8 位或8M 16 位两种
结构它的Vcc 为3.3V 其NAND 单元为固态海量存储器市场提供了最低成本的方案528 字节8 器
件或264 字16 器件的页编程操作时间为200us 16K 字节8 器件或8K 字16 器件的块
擦除操作时间为2ms 页面的数据以每个字8 器件或16 器件50ns 的速度被读出I/O 管脚可用作地
址线数据输入/输出口以及命令输入口片内写控制自动实现所有编程和擦除功能包括脉冲的周期内
部校验和数据冗余主要需要写操作的系统也可利用K9F28XXU0C 的100K 可靠的编程/擦除周期通过提
供实时描述算法得出的ECC 错误校验码特性来实现
对于诸如固态文件存储和其它需要非易失性存储器的手持式应用等大量非易失性存储器应用使用
K9F28XXU0C 器件可轻松实现.-k9f28xxu0c Chinese data Manual
16M 8 8M 16- bit NAND Flash memory K9F28XXU0C
Platform: |
Size: 751616 |
Author: tang hu |
Hits:
Description: This manual describes SAMSUNG s S3C2412-This manual describes SAMSUNG s S3C2412X 16/32-bit RISC microprocessor. This product is designed to
provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2412X includes the following
components separate 8KB Instruction and 8KB Data Cache, MMU to handle virtual memory management, LCD
Controller (65K CSTN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM
Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen
Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.
Platform: |
Size: 3121152 |
Author: kever |
Hits: