Search - opencore fpga

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[VHDL-FPGA-Verilog] video_from_opencore DL : 0: 全电视信号编码器，verilog的，看看有借鉴价值否？-video signal encoder, Verilog, to see whether the reference value?
Update : 2025-03-15 Size : 149kb Publisher : 12
[VHDL-FPGA-Verilog] sARM7TM DL : 0: ARM7TM core源码，此码来自于opencore组织，此组织免费提供一些IP core，都是一些老外写的。-ARM7TM core source, the code from opencore organizations, this organization provided free IP core, are written by foreigners.
Update : 2025-03-15 Size : 69kb Publisher :
[VHDL-FPGA-Verilog] wb_conbus.tar DL : 0: wishbone 源代码，opencore-wishbone source code, opencore
Update : 2025-03-15 Size : 15kb Publisher : 姚卫忠
[VHDL-FPGA-Verilog] opencore DL : 0: 基于FPGA的视觉采集系统的实现，verilog源码-FPGA-based visual collection system, verilog source
Update : 2025-03-15 Size : 2.07mb Publisher : www
[VHDL-FPGA-Verilog] I2C_code DL : 0: 与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。-I2C-Master Core
Update : 2025-03-15 Size : 3.11mb Publisher : summerooooo
[VHDL-FPGA-Verilog] wishbone DL : 0: Wishbone规范具有如下特点:简单、紧凑，需要很少的逻辑门完整的普通数据据传输总线协议，包括单个读写、快传输、读一修改一写周期、事件周期数据总线宽度可以是8-64位支持大端(big-endian)和小端(litle-endian)，接口自动完成两者之间的转换。支持存储器映射、FIFO存储器、交叉互联握手协议，允许速率控制可以达到每个时钟周期进行一次数据传输支持普通周期结束、重试结束、错误结束等总线周期形式支持用户自定义的标志:采用MASTER/SLAVE体系结构支持多点进程(Multi-MASTER):仲裁算法用于定义支持各种各样的IP核互联，包括USB、双向总线、复用器互联等同步逻辑设计非常简单的时序标准与硬件实现技术无关(FPGA, ASIC等) 与设计工具无关。相对于其他的IP核接口规范来说，Wishbone接口规范具有简单、开放、高效、利于实现等特点而且完全免费，并没有专利保护。基于上述优点，因此采用Wishbone总线进行接口设计。本文对Wishbone总线接口的设计参考了OpenCore上的有关设计。- Wishbone specification has the following characteristics : a simple , compact, and requires very little logic gates complete common data bus data transfer protocols, including single reader , fast transmission, read-modify- write cycle, the event cycle data bus width can be 8-64 bit support big-endian (big-endian) and the small end (litle-endian), the interface automatically convert between the two. Support memory mapping , FIFO memory , cross interconnection handshake protocol that allows rate control every clock cycle to achieve a data transfer support normal cycle ends , retry the end , wrong end of the bus cycle and other forms support for user-defined flags : The MASTER/SLAVE architecture supports multi- process (Multi-MASTER): arbitration algorithm is used to define support a variety of IP cores interconnected , including USB, bi-directional bus , multiplexer interconnection , etc. synchronous logic design very simple timing standards technology-indepe
Update : 2025-03-15 Size : 12kb Publisher : 程浩武
[Other] fpga_noc.tar DL : 0: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Update : 2025-03-15 Size : 1.59mb Publisher : 黄锦辉
[Other] fpga_NOC_mpsoc DL : 0: fpga实现的片上网络代码，代码很齐全，有文档，是从opencore上下载下来的-fpga realize on-chip network code, the code is complete, the document is downloaded the opencore down
Update : 2025-03-15 Size : 1.76mb Publisher : 黄锦辉
[Other] m16c5x_latest.tar DL : 0: PIC的8位单片机的源码，芯片16CX的源代码，摘自opencore的源代码，真实可用的- This project demonstrates the use of a PIC16C5x-compatible core as an FPGA- based processor. It implements the 12-bit instruction set, the timer 0 module, the pre-scaler, and the watchdog timer.
Update : 2025-03-15 Size : 167kb Publisher : zhang