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[JSP/Java] paobiao

Description: JAVA中定时器的运用，模拟秒表的功能进行计数
Platform: | Size: 1408 | Author: 林枫 | Hits:

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 951 | Author: 李兵 | Hits:

[Other resource] paobiao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。
Platform: | Size: 156342 | Author: 李华 | Hits:

[Embeded-SCM Develop] paobiao

Description: 用verilog写的跑表程序--Stopwatch program written by verilog.
Platform: | Size: 1024 | Author: | Hits:

[JSP/Java] paobiao

Description: JAVA中定时器的运用，模拟秒表的功能进行计数-In the use of JAVA timers, analog stopwatch functions counting
Platform: | Size: 1024 | Author: 林枫 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 软件开发环境：ISE 7.1i 仿真环境：ModelSim SE 6.0 1. 这个实例实现通过ModelSim工具实现一个具有“百分秒，秒，分”计时功能的数字跑表； 2. 工程在project文件夹中，双击paobiao.ise文件打开工程； 3. 源文件在rtl文件夹中，paobiao.v为设计文件，paobiao_tb.tbw是仿真测试文件； 4. 打开工程后，在工程浏览器中选择paobiao_tb.tbw，在Process View中双击“Simulation Behavioral Model”选项，若正确安装ModelSim，系统将自动打开ModelSim进行行为仿真，运行仿真即可得到仿真结果。-Software development environment: ISE 7.1i simulation environment: ModelSim SE 6.01. Realize this instance through the ModelSim tool realize a
Platform: | Size: 155648 | Author: 李华 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 给出了数字跑表的源代码，设计了分频模块，实现了真实的时间计数，通过这个工程的训练，能更好的了解Quartus II数字电路开发的过程。-Digital stopwatch given the source code, design the sub-frequency module, the realization of the true count of time, through this project the training, to better understand the Quartus II development of the process of digital circuits.
Platform: | Size: 237568 | Author: 张应辉 | Hits:

[Linux-Unix] paobiao.v

Description: 秒表，可暂停，计时，复位，在cadence上运行仿真 -Stopwatch, may be suspended, timing, reset, run simulation in cadence
Platform: | Size: 1024 | Author: minglang | Hits:

[Other] paobiao

Description: 用硬件描述语言编写的跑表程序。实现了跑表秒到分的记时。-Using hardware description languages stopwatch procedure. Seconds to achieve a stopwatch when the entry points.
Platform: | Size: 1024 | Author: 格格 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个基于FPGA的数字跑表系统的设计，最小单位是百分表位。采用十进制进位。-FPGA-based digital stopwatch system design, the smallest unit is a digital dial indicator. Binary using the metric system.
Platform: | Size: 44032 | Author: jyb | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: verilog实现的数字跑表 精确到10ms-verilog digital stopwatch to achieve accurate to 10ms
Platform: | Size: 2048 | Author: 李丹 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 一个用verilog编的时钟程序A clock with the procedures for verilog-A clock with verilog program for A clock with the procedures for verilog
Platform: | Size: 295936 | Author: lee | Hits:

[Embeded-SCM Develop] paobiao

Description: 1)利用51单片机作为主控制器组成一个电子跑表，采用4位LED显示器。 2)上电或RESET后显示000.0。 3)当按下START键时，作为跑表使用，显示范围是：000.0-999.9秒，当按下STOP键时，跑表停止运行，并保留所停位置的时间显示不变。-1) the use of 51 single-chip microcomputer as the master controller of an electronic stopwatch, the four LED displays. 2) after the power or RESET display 000.0. 3) When pressing the START button, the stopwatch as the use, display range is :000.0-999 .9 seconds, when pressing the STOP button, the stopwatch to stop running, and to retain the location of the stop show the same time.
Platform: | Size: 1024 | Author: 张宇 | Hits:

[CSharp] paobiao

Description: 实现跑表的一个示例，这是根据书上的示例经过自己调试的．-An example of the realization of the stopwatch, which is based on the book through their own examples of debugging.
Platform: | Size: 28672 | Author: dick | Hits:

[Software Engineering] paobiao

Description: 实现数字跑表功能，该跑表具有复位、暂停、秒表计时等功能。-Digital stopwatch function, the stopwatch with a reset, pause, stopwatch timer functions.
Platform: | Size: 483328 | Author: 刘新 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 数字跑表，VHDL语言描述，已经过实验,包含有分频计、计数器，显示译码器-It has been tested,and it is described by VHDL.
Platform: | Size: 862208 | Author: 高建双 | Hits:

[VHDL-FPGA-Verilog] paobiao

Description: 基于Verilog HDL的完整数字跑表工程，在试验机台上运行验证通过了的。 用8位7段数码管分别显示微妙，秒，分。 有开始，暂停，复位功能。 学习VerilogHDL的经典例子，添加了显示功能。-Complete Verilog HDL-based digital stopwatch works in the test machine is running verify pass the platform. With 8-bit 7-segment digital tube showed the delicate, seconds, minutes. Has started, pause, reset. Learning VerilogHDL classic example of adding a display.
Platform: | Size: 571392 | Author: alvin | Hits:

[Other Embeded program] paobiao

Description: 基于stc89c51 的单片机的跑表设计，计时准确，带有防偷跑功能。-Microcontroller-based stc89c51 the stopwatch design, timing accuracy, with anti-Unleashed features.
Platform: | Size: 1024 | Author: xuzhijian | Hits:

[SCM] paobiao

Description: 用单片机实现跑表功能 由0——999计数 以1 的速度运行-With the single chip microcomputer PaoBiao functions by 0 running to 999 to 1 of the speed of operation punch the three are reset
Platform: | Size: 1024 | Author: 武云钢 | Hits:

[Software Engineering] digital-paobiao

Description: 是在50M CLK 下实现的，通过在数码管上实现进位显示-Digital PaoBiao，which works in the 50 M CLK is under implementation, through pipes in the digital realization that carry
Platform: | Size: 398336 | Author: 唐雅 | Hits:
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