Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - parity check vhdl

Search list

[Communication-Mobile] DECODE

Description: 低密度奇偶校验码即LDPC码的译码C程序，码长为16位-Low-density parity-check code that is decoding LDPC codes C procedures, code length of 16
Platform: | Size: 1024 | Author: 赵天婵 | Hits:

[Crack Hack] crc

Description: 此源代码实现了CRC5和CRC16的校验以及校验码的产生，可以直接用于RFID标签数字电路。-This source code CRC5 and realize the CRC16 checksum and the emergence of parity-check codes, RFID tags can be directly used for digital circuits.
Platform: | Size: 2048 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] checkNodee_Behavioral_VHDL

Description: LDPC码校验节点（checknode）进行奇偶校验方程时的vhdl编程，硬件语言实现-LDPC check nodes (checknode) carried out at the time of parity equation VHDL programming, hardware language
Platform: | Size: 1024 | Author: 王明 | Hits:

[matlab] LDPCBSN

Description: LDPC码既低密度奇偶校验码（Low Density Parity Check Code，LDPC），它由Robert G.Gallager博士于1963年提出的一类具有稀疏校验矩阵的线性分组码，不仅有逼近Shannon限的良好性能，而且译码复杂度较低, 结构灵活，是近年信道编码领域的研究热点，目前已广泛应用于深空通信、光纤通信、卫星数字视频和音频广播等领域。LDPC码已成为第四代通信系统(4G) -LDPC codes BER simulation under AWGN channel. MacKay-Neal based LDPC matrix. Message encoding uses sparse LU decomposition. There are 4 choices of decoder: hard-decision/bit-flip decoder, probability-domain SPA decoder, log-domain SPA decoder, and simplified log-domain SPA decoder.
Platform: | Size: 8192 | Author: 天天 | Hits:

[Industry research] VLSI_Architectures_for_ECC

Description: This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.
Platform: | Size: 1072128 | Author: MicroSam | Hits:

[Documents] Encoders_for_Block_Circulant_LDPC_Codes

Description: In this paper, we present two encoding methods for block-circulant LDPC codes. The first is an iterative encoding method based on the erasure decoding algorithm, and the computations required are well organized due to the blockcirculant structure of the parity check matrix.
Platform: | Size: 394240 | Author: kumar | Hits:

[VHDL-FPGA-Verilog] Realization_of_FPGA_for_LDPC_encoding

Description: 低密度奇偶校验码(简称LDPC码)是目前距离香农限最近的一种线性纠错码，它的直接编码运算量较大，通常具有码长的二次方复杂度．为此，利用有效的校验矩阵，来降低编码的复杂度，同时研究利用大规模集成电路实现LDPC码的编码．在ISE 8．2软件平台上采用基于FPGA的Verilog HDL语言实现了有效的编码过程，为LDPC码的硬件实现和实际应用提供了依据-Abstract：Low．density parity·check code(LDPC code)is a kind of linear eror·correcting code nearest to Shannon Limit．For LDPC cod e，the computational overhead for direct encoding operations is large，as the complexity of encod ing is the square of the length of codeword．Hence，this paper reduces the complexity of coding by using effective parity—check matrix，and realizes the encoding device for LDPC code by use of large·scale integrated circuits．The effective encoding process based on FPGA with Verilog HDL language is implemented on ISE 8．2 software platform ，providing a feasible basis for hardware implementation an d practical application of LDPC code．
Platform: | Size: 165888 | Author: 秦小星 | Hits:

[VHDL-FPGA-Verilog] uart-VHDL

Description: uart-VHDL 带奇偶校验位 比特率为1152-uart-VHDL add parity check bit rate is 115200
Platform: | Size: 5120 | Author: | Hits:

[VHDL-FPGA-Verilog] parity_chk_32

Description: 这是一个32位的奇偶校验程序,VHDL代码,可用于FPGA.-32 bit parity check
Platform: | Size: 1024 | Author: 周君 | Hits:

[VHDL-FPGA-Verilog] parity_chk_32-

Description: 这是一个用在FPGA上的, VHDL源码, 32位奇偶校验程序.-32 bit parity check
Platform: | Size: 1024 | Author: 周君 | Hits:

[VHDL-FPGA-Verilog] PARITY-CHECK

Description: this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv -this vhdl code for parity check is very helpful while coding and decoding , Implementing this in an cpld of fpga is very easy and it can be used as a subpart of any embededd design such as multiplexers , Decoders etcv
Platform: | Size: 8192 | Author: srivhdl | Hits:

CodeBus www.codebus.net