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[Other] PhaseLockedLoop DL : 0: phase lock loop for coherent detection
Update : 2008-10-13 Size : 2.52kb Publisher : benny
[Communication] gfuzzy DL : 0: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
Update : 2008-10-13 Size : 33.21kb Publisher : gogomx
[VHDL-FPGA-Verilog] 数字锁相环 DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-digital phase-locked loop PLL design source, in which Fi is the input frequency (receive data), Fo (Q5) is the local output frequency. Objective is to extract data input clock signal (Q5), its frequency and data rate line, the clock rising edge of the lock data the rising and falling edge; top-level document is PLL.GDF
Update : 2025-03-15 Size : 122kb Publisher : 于洪彪
[Other] PhaseLockedLoop DL : 0: phase lock loop for coherent detection
Update : 2025-03-15 Size : 2kb Publisher : benny
[Program doc] PLL_PLV DL : 0: 锁相回路可视为一个输出相位和输入相位的回授系统用以同步输入参考讯号和回授后输出信号。并让其操作同样的频率。如(图一)所示，简单锁相回路[3,4]是由三个电路构成，分别为相位侦测器（Phase Detector）、回路滤波器（Loop Filter）、压控荡器（VCO）-phase-locked loop can be regarded as a phase output and input phase feedback system for synchronous reference input and feedback signals After the output signal. And allowed to operate the same frequency. If (Figure 1), the simple lock-loop [3,4] by the three circuit. for the detection phase (Phase Detector), loop filter (Loop Filter), VCO finishes (VCO)
Update : 2025-03-15 Size : 146kb Publisher : 王浩
[Software Engineering] matlab DL : 0: pll锁相环仿真程序，经过测试，并附上仿真图，值得学习-pll phase locked loop simulation program, tested with the simulation map, it is worth learning
Update : 2025-03-15 Size : 1kb Publisher : james
[DSP program] CAlgorithmsofdsp DL : 0: DSP常用C语言算法，适合入门和中级用户。
Update : 2025-03-15 Size : 1.24mb Publisher :
[Communication] gfuzzy DL : 0: 基于模糊逻辑控制的数字锁相环，用于通信系统中的载波恢复。Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.-Based on fuzzy logic control of digital phase-locked loop for the communication system in carrier recovery. Digital phase lock loop base on fuzzy logical control, which is used to recover carrier in communication system.
Update : 2025-03-15 Size : 33kb Publisher : gogomx
[VHDL-FPGA-Verilog] DPLL(VHDL) DL : 0: 使用VHDL语言进行的数字锁相环的设计，里面有相关的文件，可以使用MUX+PLUS打开-The use of VHDL language of digital phase-locked loop design, there are relevant documents, you can use MUX+ PLUS Open
Update : 2025-03-15 Size : 13kb Publisher : 国家
[VHDL-FPGA-Verilog] PLL DL : 0: PLL是数字锁相环设计源程序, 其中, Fi是输入频率(接收数据), Fo(Q5)是本地输出频率. 目的是从输入数据中提取时钟信号(Q5), 其频率与数据速率一致, 时钟上升沿锁定在数据的上升和下降沿上；顶层文件是PLL.GDF-Digital phase-locked loop PLL is the design source code, which, Fi is the input frequency (receive data), Fo (Q5) is a local output frequency. The purpose is to extract data from the input clock signal (Q5), their frequency and data rate in line clock rising edge of lock-in data on rising and falling edge PLL.GDF top-level document
Update : 2025-03-15 Size : 124kb Publisher : 许伟
[Other] PhaseLockLoop DL : 0: This book introduces the basics of Phase Lock Loop and the design problems.
Update : 2025-03-15 Size : 316kb Publisher : NANCY LU
[Industry research] PLLdesign DL : 0: This document includes the statements on the basics of Phase Lock Loop problems, control, and design methods.
Update : 2025-03-15 Size : 346kb Publisher : NANCY LU
[matlab] synchronization DL : 0: 采用AFC技术来锁定频，采用Garden技术进行定时恢复，采用Costas环进行相位的锁定-Use technology to lock the frequency of AFC, using Garden timing recovery techniques using Costas loop for phase locking
Update : 2025-03-15 Size : 3kb Publisher : caomin
[Other] Principles_and_Applications_of_PLL DL : 0: 锁相技术，老版的电子书，有三阶锁相环的内容。现在的书讲三阶锁相环的不多，找了好久。-Technology of PLL（Phase Lock Loop）, the old version of the PLL series book. The valueable part is contents of third-order PLL.,which is not found easily in other books.
Update : 2025-03-15 Size : 5.29mb Publisher : fengyang
[matlab] PLL_ars DL : 0: phase lock loop method
Update : 2025-03-15 Size : 7kb Publisher : arslan
[Technology Management] PLL-phase-lock-loop-application DL : 0: 锁相环PLL原理与应用，锁相环PLL原理与应用-PLL phase lock loop principle and application
Update : 2025-03-15 Size : 227kb Publisher : 姚
[Other] pll DL : 0: phase lock loop amjadmftah@hotmail.com
Update : 2025-03-15 Size : 180kb Publisher : amjad
[Other] digital-phase-locked-loop- DL : 0: 基于FPGA的数字锁相环的研究与实现,锁相速度快。-The study of the digital phase-locked loop based on FPGA and implementation, fast phase lock.
Update : 2025-03-15 Size : 1.18mb Publisher : 安慧林
[Software Engineering] inverters-without-phase-lock-loop DL : 0: 不平衡电网下无锁相环三相并网逆变器控制策略-inverters without phase-lock loop
Update : 2025-03-15 Size : 919kb Publisher : kamida
[matlab] phase-lock-loop DL : 0: 编制Matlab仿真程序。通过计算机仿真比较可以得出动态（捕获）性能，并画出改变某个参数条件下的响应曲线，根据仿真结果更加直观、系统地分析环路的动态性能，为采样锁相环的研究和工程设计提供参考。 -Through the computer simulation comparison can be obtained dynamic (capture) performance, and draw a change under a certain parameter conditions According to the simulation results, the dynamic performance of the loop is systematically analyzed, and the research of the phase locked loop is studied. Engineering design for reference.
Update : 2025-03-15 Size : 3kb Publisher : 廖

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