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Description: 一个模拟管道流动的ACTIVEX控件-a simulated pipeline flow ACTIVEX control
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Size: 44032 |
Author: 刘明法 |
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Description: 1. 编写一个C程序作为Linux内核的shell命令行解释程序。Shell程序应该使用与Bource shell相同的方式运行程序。 2. 增加功能以使用户可以使用"&"操作符作为命令的结束符。一个以"&"结尾的命令应该与shell并发执行。 3. 增加功能以使用户可以使用"<"和">"作为文件名前缀来重定向stdin和stdout描述符。同样，允许用户使用管道操作符" "来同时执行两个进程，并把第一个进程的stdout重定向为第二个进程的stdin。-1. Preparation of a C program as a Linux kernel shell command line interpreter. Shell procedures should be used with Bource shell the same way as operational procedures. 2. Increased functionality so that customers can use, "" operator, as ordered by the end tags. A "" the end of the order should be concurrent with the implementation of the shell. 3. Increased functionality so that customers can use "lt;" "Gt;" As a filename prefix to redirect stdin and stdout descriptors. Similarly, allows users to use pipeline operator, "" two parallel processes, and a process to redirect stdout second process stdin.
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Size: 22528 |
Author: 李强 |
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Description: 一个三维gis管线的源代码
做三维管线gis的开发人员可以参考下-a 3D pipeline gis the source code to do 3D pipeline gis developers can refer to the next
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Size: 545792 |
Author: 王涛 |
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Description: 关于FPGA流水线设计的论文
This work investigates the use of very deep pipelines for
implementing circuits in FPGAs, where each pipeline
stage is limited to a single FPGA logic element (LE). The
architecture and VHDL design of a parameterized integer
array multiplier is presented and also an IEEE 754
compliant 32-bit floating-point multiplier. We show how to
write VHDL cells that implement such approach, and how
the array multiplier architecture was adapted. Synthesis
and simulation were performed for Altera Apex20KE
devices, although the VHDL code should be portable to
other devices. For this family, a 16 bit integer multiplier
achieves a frequency of 266MHz, while the floating point
unit reaches 235MHz, performing 235 MFLOPS in an
FPGA. Additional cells are inserted to synchronize data,
what imposes significant area penalties. This and other
considerations to apply the technique in real designs are
also addressed.-FPGA pipelined designs on paper This work investigates the use of very deep pipelines forimplementing circuits in FPGAs, where each pipelinestage is limited to a single FPGA logic element (LE). Thearchitecture and VHDL design of a parameterized integerarray multiplier is presented and also an IEEE 754compliant 32-bit floating-point multiplier. We show how towrite VHDL cells that implement such approach, and howthe array multiplier architecture was adapted. Synthesisand simulation were performed for Altera Apex20KEdevices, although the VHDL code should be portable toother devices. For this family, a 16 bit integer multiplierachieves a frequency of 266MHz, while the floating pointunit reaches 235MHz, performing 235 MFLOPS in anFPGA. Additional cells are inserted to synchronize data, what imposes significant area penalties. This and otherconsiderations to apply the technique in real designs arealso addressed.
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Size: 179200 |
Author: 李中伟 |
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Description: Pipeline synchronization is a simple, low-cost, highbandwidth,highreliability solution to interfaces between synchronous and asynchronous systems, or between
synchronous systems operating from different clocks.-Pipeline synchronization is a simple, low-cost, highbandwidth. highreliability solution to interfaces betwe en synchronous and asynchronous systems, or between synchronous systems operating from different clocks.
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Size: 855040 |
Author: 叶艳 |
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Description: 主要介绍算法的实现方式和流水线实现，而且有详细的原理介绍，推理，源码和仿真结果-The main way of introduction Algorithm and pipelining to achieve, but also has a detailed introduction of the principle, reasoning, source code and simulation results
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Size: 162816 |
Author: 李佳 |
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Description: 输油管道问题，用文件的方式，用的是分而治之的思想-Pipeline problems, and use of papers, using a divide and rule ideology
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Size: 230400 |
Author: kobewylb |
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Description: 2004版witness的自带模型，比较复杂，一个是流水线，一个是港口模型。非常实用-Witness s own 2004 version of the model, more complicated, a pipeline, a port model. Very useful
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Size: 31744 |
Author: ninaxie |
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Description: cordic IP core
Features
Each file is stand-alone and represents a specific configuration.
The 4 parameters are:
Rotation or Vector Mode
Vector Precision
Angle Precision
Number of Cordic Stages
All designs are pipelined with a synchronous enable and reset.
The pipeline latency equals 2 clock cycles plus the number of cordic stages.
The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.v
r : Cordic Mode. r = Rotation, v = Vectoring
32 : Precision of the individual vector components.
16 : Precision of the angle.
12 : Number of cordic stages.
Current configurations:
cf_cordic_r_8_8_8
cf_cordic_v_8_8_8
cf_cordic_r_16_16_16
cf_cordic_v_16_16_16
cf_cordic_r_18_18_18
cf_cordic_v_18_18_18
cf_cordic_r_32_32_32
cf_cordic_v_32_32_32-cordic IP coreFeatures Each file is stand-alone and represents a specific configuration. The 4 parameters are: Rotation or Vector Mode Vector Precision Angle Precision Number of Cordic Stages All designs are pipelined with a synchronous enable and reset. The pipeline latency equals 2 clock cycles plus the number of cordic stages. The configuration parameters are coded in the file names: cf_cordic_r_32_16_12.vr: Cordic Mode. r = Rotation, v = Vectoring 32: Precision of the individual vector components. 16: Precision of the angle. 12: Number of cordic stages. Current configurations: cf_cordic_r_8_8_8 cf_cordic_v_8_8_8 cf_cordic_r_16_16_16 cf_cordic_v_16_16_16 cf_cordic_r_18_18_18 cf_cordic_v_18_18_18 cf_cordic_r_32_32_32 cf_cordic_v_32_32_32
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Size: 457728 |
Author: abcoabco |
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Description: 一个使用匿名管道进行通信的示例程序，重点是管道是单向的，进行读写需要建立两个管道。-A pipeline to carry out the use of anonymous communications sample programs, with a focus on pipeline is one-way, to read and write need to build two pipelines.
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Size: 2048 |
Author: lht |
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Description: 用于简单管道的水击计算，采用的特征线法。可自行修改管道参数。-For a simple pipeline water hammer calculation, using the characteristic line method. Pipeline can modify the parameters.
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Size: 11264 |
Author: chenchen82 |
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Description: SIMULINK® MODEL FOR SIMULATION OF A 14-BIT PIPELINE ADC-SIMULINK ? MODEL FOR SIMULATION OF A 14-BIT PIPELINE ADC
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Size: 107520 |
Author: 张海 |
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Description: 关于FPGA设计中的流水线技巧的使用和例子，一个很好的减少硬件消耗的技巧-About FPGA design using pipelining techniques and examples, a good technique to reduce the hardware consumption
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Size: 1028096 |
Author: JET |
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Description: FIFO先进先出队列，一种缓存、或一种管道、设备、接口（Verilog HDL程序,内附说明）-FIFO FIFO queue, a cache, or a pipeline, equipment, Interface (Verilog HDL program, containing a note)
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Size: 5120 |
Author: 镜子 |
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Description: Description of a pipeline architecture for a FFT processor, based on the R22SDF algorithm.
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Size: 194560 |
Author: rhadookoo |
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Description: 采用fpga做小数运算的程序，使用了三级流水线技术，这是学习流水线和定点小数乘法很好的例子！-a program of float multiply, using 3-stage pipeline technology
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Size: 1024 |
Author: xietianjiao |
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Description: GPU Gems is a compilation of articles covering practical real-time graphics techniques arising from the research and practice of cutting-edge developers. It focuses on the programmable graphics pipeline available in todays graphics processing units (GPUs) and highlights quick and dirty tricks used by leading developers, as well as fundamental, performance-conscious techniques for creating advanced visual effects. The contributors and editors, collectively, bring countless years of experience to enlighten and propel the reader into the fascinating world of programmable real-time graphics.
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Size: 14535680 |
Author: mike |
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Description: 这是一个用Verilog编写的四级流水线加法器-This is a Verilog prepared with four pipeline adder
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Size: 1024 |
Author: 伊莲幽梦 |
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Description: 该文档提出了一种应用于开关电容流水线模数转换器的CMoS预运放一锁存比较
器．该比较器采用UMC混合／射频0．18肛m 1P6M P衬底双阱CMOS工艺设计，工作电压为
1．8 V．该比较器的灵敏度为0．215 mV，最大失调电压为12 mV，差分输入动态范围为1．8
V，分辨率为8位，在40 M的工作频率下，功耗仅为24．4 ttW．基于0．18 gm工艺的仿真结
果验证了比较器设计的有效性．-A CMOS preamplifier-latch comparator used in switched··capacitor pipeline analog··to-digital con·-
verter WBS presented．The comparator WaS d髑igned under UMC Mixed．Mode／RF 0．18 btm 1P6M P．Sub Twin—
Well CMOS process and worked with 1．8V power supply．The sensitivity of the comparator was 0．215 mV，
the largest offset voltage was 12 mV，the differentiaI input range Was 1．8 V，the resolution was 8 bit and the
power dissipation Was only 24．4 gW at 40 MHz．HSPICE simulations of the comparator implemented in a 0．18
um technology demonstrate its effectiveness．
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Size: 361472 |
Author: 赵恒 |
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Description: Auto-filling of Summary Result Tables of Offshore Pipeline A&R and Normal Laying Analysis using MATLAB
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Size: 327680 |
Author: zaragooza |
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