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[VHDL-FPGA-Verilog] pipe

Description: verilog编写的流水线模块-Verilog modules prepared by the Pipeline
Platform: | Size: 5120 | Author: 刘陆陆 | Hits:

[OS program] dlx

Description: mips pipeline 模以程序，mfc实现的，功能就不用说了把，大家都知道的-MIPS pipeline to die procedures mfc achieve, and functions not have had to put, we all know the
Platform: | Size: 24576 | Author: 吴动 | Hits:

[ARM-PowerPC-ColdFire-MIPS] Pipeline模拟

Description: 计算机体系结构中关于通用5级流水线的模拟实现程序-computer architecture on the common five Pipeline Simulation procedures
Platform: | Size: 421888 | Author: 欧未然 | Hits:

[Software Engineering] loongson

Description: 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月 龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指 令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件 中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原 来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Computing Technology agreed that the semiconductor companies in 2006 9 Godson 2 on E processor is one realization of 64 MIPS Instruction Set III generic RISC processor. Godson 2 E. pipelined instructions every clock cycle from four decoding instructions, Dynamic and fired five full pipeline of functional components. Although the directive in ensuring dependence carried out under the premise of Out-of-order execution, However, the directive is to follow the procedures of the original order to ensure accurate and interrupted his visit to the implementation of the order deposit.
Platform: | Size: 1141760 | Author: BQT | Hits:

[Software Engineering] Godson1

Description: 龙芯一号的数据手册！ 通用32 位微处理器，支持MIPS-III 指令 主频为200~266MHZ 基于操作队列复用的高效7 级标量流水线 高效的64 位浮点流水单元 浮点性能220 MFLOP @250MHz 内置MMU、TLB 实现从程序虚拟地址到CPU物理地址的转换-Godson manual data on the 1st! Definitive 32 microprocessor, support MIPS-III Directive megabyte of 200-266MHZ operation based cohort efficient reuse of seven scalar Pipeline efficient 64-bit floating-point pipeline unit 220 MFLOP floating point performance @ 250MHz embedded MMU. TLB realization procedures virtual address to the CPU physical address translation
Platform: | Size: 313344 | Author: lsj | Hits:

[JSP/Java] MipsSimulator

Description: 实现一个具有5段流水线结构的Mips-lite模拟器，该模拟器结构具有data forwarding，stall 处理等功能-The realization of a pipeline structure with paragraph 5 of the Mips-lite simulator, the simulator structure of data forwarding, stall and other functions to deal with
Platform: | Size: 285696 | Author: Draco | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: mips处理器指令仿真器，可查看流水线执行方式-mips instruction processor emulator, you can review the pipeline implementation
Platform: | Size: 991232 | Author: 魏继增 | Hits:

[VHDL-FPGA-Verilog] DES_IP

Description: 有效的改进3-DES算法的执行速度，采用了多级流水线技术，设计了一种高速的硬件结构，使得原来需要48个时钟周期才能完成的运算，现在只需要一个时钟周期就可以完成。另外通过增加输入/输出的控制信号。使得该IP可以方便的集成到SOC中，大大缩短了SOC的设计周期。-Effective 3-DES algorithm to improve the implementation of speed, multi-stage pipeline technology, designed a high-speed hardware architecture, making the original 48 clock cycles required to complete the operation, and now only need one clock cycle can be completed. In addition by increasing the input/output control signal. Makes the IP can be easily integrated into the SOC, the SOC has significantly shortened the design cycle.
Platform: | Size: 23552 | Author: charity | Hits:

[ARM-PowerPC-ColdFire-MIPS] MIPS

Description: 带分支预测的MIPS流水线的verilog原代码。 详细介绍了流水线的设计代码-Branch prediction with the MIPS pipeline verilog source code. Details of pipeline design code
Platform: | Size: 17408 | Author: 张鹤 | Hits:

[ARM-PowerPC-ColdFire-MIPS] pipeline

Description: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Platform: | Size: 3028992 | Author: kevin | Hits:

[OS program] MIPS

Description: MIPS-lite Simulator 流水线模拟器实现-MIPS-lite Simulator pipeline simulator to achieve
Platform: | Size: 5787648 | Author: wang | Hits:

[Embeded-SCM Develop] mips

Description: 在maxplus上实现了一个5级流水线的mips cpu，含cache-In maxplus to achieve a 5-stage pipeline of the mips cpu, with cache
Platform: | Size: 449536 | Author: tong tong | Hits:

[VHDL-FPGA-Verilog] vhdl-pipeline-mips_latest.tar

Description: pipeline mips in vhdl
Platform: | Size: 1137664 | Author: aliakbar | Hits:

[VHDL-FPGA-Verilog] PipeLine.tar

Description: Verilog实现MIPS五段流水线，22条指令（基本算术、移位和load、store指令），模块化设计，含注释-Verilog realization of five-stage pipeline MIPS 22 instructions (basic arithmetic, shift, and load, store instructions), modular design, with annotations
Platform: | Size: 2929664 | Author: czl | Hits:

[VHDL-FPGA-Verilog] mips

Description: mips pipeline code.. copyright material for fr-mips pipeline code.. copyright material for free
Platform: | Size: 8192 | Author: puneet | Hits:

[VHDL-FPGA-Verilog] pipelined-mips-cpu

Description: 用verilog语言描述了MIPS的5级流水线。-Language described by verilog MIPS 5-stage pipeline.
Platform: | Size: 171008 | Author: jack chen | Hits:

[VHDL-FPGA-Verilog] mips

Description: pipeline mips processor
Platform: | Size: 2650112 | Author: aden | Hits:

[VHDL-FPGA-Verilog] Pipelined-MIPS

Description: MIPS架构5级流水线设计，支持常用的整数指令。-5-stage pipeline MIPS architecture designed to support common integer instructions.
Platform: | Size: 183296 | Author: txh | Hits:

[VHDL-FPGA-Verilog] MIPS

Description: 5个stage的pipeline MIPS，支持着JUMP，BRANCH等跳转命令。-simple 5-stages MIPS structure which supports forwarding commands.
Platform: | Size: 14336 | Author: Taowu | Hits:

[ARM-PowerPC-ColdFire-MIPS] PipelineCPU

Description: 1. understand how to improve CPU performance 2. master the working principle of pipelined MIPS microprocessor. 3. understand the concept of data adventure, control risk and the solution of pipeline conflict. 4. mastering the testing method of pipelined MIPS microprocessor(this file contains 3 packs,which is developed in Xilinx ISE contain the basic functions of a typical CPU 5 stages:IF,ID,EX,MEM,WB for education only)
Platform: | Size: 633856 | Author: D.FRANCIS | Hits:
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