Description: 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月
龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指
令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件
中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原
来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Computing Technology agreed that the semiconductor companies in 2006 9 Godson 2 on E processor is one realization of 64 MIPS Instruction Set III generic RISC processor. Godson 2 E. pipelined instructions every clock cycle from four decoding instructions, Dynamic and fired five full pipeline of functional components. Although the directive in ensuring dependence carried out under the premise of Out-of-order execution, However, the directive is to follow the procedures of the original order to ensure accurate and interrupted his visit to the implementation of the order deposit. Platform: |
Size: 1141809 |
Author:BQT |
Hits:
Description: 一个TIDM642DSP处理器测试程序，分别用C和ASM编写，ASM分别用10~6个循环实现，适宜学习流水线编程手段和熟悉汇编命令-a TIDM642DSP processor test procedures were used to prepare C and ASM. ASM respectively 10 ~ 6 cycling and appropriate learning tools and programming pipeline familiar with the compilation of orders Platform: |
Size: 15741 |
Author:赵鑫 |
Hits:
Description: 龙芯2E处理器用户手册 中国科学院计算技术研究所 意法半导体公司 2006年 9 月
龙芯2E处理器是一款实现64位MIPS III 指令集的通用RISC处理器。龙芯2E的指
令流水线每个时钟周期取四条指令进行译码，并且动态地发射到五个全流水的功能部件
中。虽然指令在保证依赖关系的前提下进行乱序执行，但是指令的提交还是按照程序原
来的顺序，以保证精确中断和访存顺序执行。 -Godson 2E processor user manual CAS Institute of Computing Technology agreed that the semiconductor companies in 2006 9 Godson 2 on E processor is one realization of 64 MIPS Instruction Set III generic RISC processor. Godson 2 E. pipelined instructions every clock cycle from four decoding instructions, Dynamic and fired five full pipeline of functional components. Although the directive in ensuring dependence carried out under the premise of Out-of-order execution, However, the directive is to follow the procedures of the original order to ensure accurate and interrupted his visit to the implementation of the order deposit. Platform: |
Size: 1141760 |
Author:BQT |
Hits:
Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing. Platform: |
Size: 9216 |
Author:李乔 |
Hits:
Description: Description of a pipeline architecture for a FFT processor, based on the R22SDF algorithm. Platform: |
Size: 194560 |
Author:rhadookoo |
Hits:
Description: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed
below.
Features
Hardware Features
• Data Path Width 32 bits, with Four stage pipeline.
• Mixed 16/32 bit instructions for code density
• Von Neumann Architecture (Data and Instruction in the same
address space).
• Sixteen, 32 bit General Purpose Registers.
• Four USER defined instructions (with Register File Write back
capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed
below.
Features
Hardware Features
• Data Path Width 32 bits, with Four stage pipeline.
• Mixed 16/32 bit instructions for code density
• Von Neumann Architecture (Data and Instruction in the same
address space).
• Sixteen, 32 bit General Purpose Registers.
• Four USER defined instructions (with Register File Write back
capability). Platform: |
Size: 3395584 |
Author:hfayed |
Hits:
Description: DLX 处理器 (发音为 "DeLuXe")是Hennessy 和Patterson合著一书《Computer Architecture - A Quantitative Approach》中流水线处理器的例子。WinDLX是一个基于Windows的模拟器。本教程通过一个实例介绍WinDLX的使用方法。WinDLX模拟器能够演示DLX流水线是如何工作的。-DLX processor (pronounced " DeLuXe" ) is Hennessy and Patterson co-book " Computer Architecture- A Quantitative Approach" in the pipeline processor example. WinDLX is a Windows-based simulator. This tutorial introduces WinDLX an example to use. WinDLX DLX pipeline simulator to demonstrate how it works. Platform: |
Size: 324608 |
Author: |
Hits:
Description: early branch rename table-store rename table once the branch instruction comes in. Used in out of order pipeline processor Platform: |
Size: 1024 |
Author:Isabella Ni |
Hits:
Search - pipeline processor