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[Other Embeded program] verilogpll

Description: 用verilog语言编写的全数字锁相环的源代码,基于fpga平台-using Verilog language prepared by the DPLL the source code, they simply based on the platform
Platform: | Size: 3072 | Author: letheo | Hits:

[VHDL-FPGA-Verilog] ADPLL

Description: verilog ADPLL file with testbench.v
Platform: | Size: 25600 | Author: | Hits:

[Wavelet] verilogpll1234

Description: 基于verilog的全数字锁相环的设计，基于verilog的全数字锁相环的设计。-verilog DPLL the design, verilog based on the DPLL design.
Platform: | Size: 93184 | Author: li | Hits:

[Software Engineering] xp2syscloclkpll

Description: 这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多-Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar
Platform: | Size: 641024 | Author: | Hits:

[Program doc] DDS

Description: FPGA中实现基于查找表方式（LUT）的DDS实现，可用在数字下变频和COSTAS锁相环中，Verilog编写，本人已经调通-In FPGA-based lookup table approach (LUT) to achieve the DDS can be used in the digital down-conversion and COSTAS PLL, Verilog prepared, I have transferred Qualcomm
Platform: | Size: 148480 | Author: | Hits:

[VHDL-FPGA-Verilog] dpll_demo

Description: 一个实现简单的数字锁相环Verilog代码，本人借鉴网上现有的代码后经修改在Cyclone II上调通实现，里面有ModelSim仿真成功的波形图-A simple digital PLL Verilog code, I draw on-line after the existing code, as amended, pass upward in the Cyclone II realized, there are successful ModelSim Simulation Waveform
Platform: | Size: 67584 | Author: | Hits:

[DSP program] PLL

Description: 可以实现自动锁相环功能的C源程序代码模块，-Can be achieved automatically PLL function C source code modules,
Platform: | Size: 6144 | Author: 刘磊 | Hits:

[VHDL-FPGA-Verilog] PLL

Description: verilog PLL的代码，和PLL 的功能介绍，希望能通过，只是简单了点-verilog PLL code, and the function of PLL, the hope, but simply a point
Platform: | Size: 18432 | Author: gjj | Hits:

[Other] pll_funcnl

Description: pll in verilog in the Appendix
Platform: | Size: 227328 | Author: jadedfox | Hits:

[Industry research] pll_verilog

Description: verilog model of a P-verilog model of a PLL
Platform: | Size: 135168 | Author: jadedfox | Hits:

[Other] pll_verilog_code

Description: 这是一段pll verilog代码，是本人转载！-This is a period of pll verilog code, yes I reprint!
Platform: | Size: 3072 | Author: 海天之洲 | Hits:

[Communication-Mobile] EP2C8_pll_example

Description: EP2C8 PLL例化的例子,给不会的人做个参考.专门写的一个.呵呵.不过是Verilog的.-EP2C8 PLL cases of the examples to those who will not be a reference. Specialized write a. Ha ha. But the Verilog.
Platform: | Size: 485376 | Author: tupeng | Hits:

[VHDL-FPGA-Verilog] dds

Description: 基于FPGA的DDS设计，本程序采用verilog HDL语言编写，使用DDS+Pll倍频-The DDS-based FPGA design, the procedures used verilog HDL language, the use of DDS+ Pll frequency
Platform: | Size: 190464 | Author: 赵一 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 用VERILOG语言实现的数字锁相环P-VERILOG language with the digital phase-locked loop PLL
Platform: | Size: 384000 | Author: 叶少朋 | Hits:

[VHDL-FPGA-Verilog] pll

Description: 实现了pll功能，有利于初学者学习pll，采用文本编辑的，利用quartus ii 设计的-Achieved pll function, help beginners learn pll, using a text editor, using quartus ii Design
Platform: | Size: 216064 | Author: ad | Hits:

[Other] PLL_Analysis

Description: 关于锁相环（PLL）的经典教程，有相关matlab仿真程序的详细说明。来自国外的十分珍贵的资料。-With regard to phase-locked loop (PLL) of the classic tutorial matlab simulation program with relevant details. From abroad is very valuable information.
Platform: | Size: 65536 | Author: yxyAlbert | Hits:

[VHDL-FPGA-Verilog] 255

Description: 全数字锁相环的Verilog源代码，经过仿真调试-All-digital PLL Verilog source code, through the simulation to debug
Platform: | Size: 154624 | Author: 张文 | Hits:

[Software Engineering] PLL(pdf)

Description: 锁相环的设计方法介绍（PLL），可作为设计的参考。-Design method for PLL (PLL), can be used as a reference design.
Platform: | Size: 73728 | Author: 李强 | Hits:

[VHDL-FPGA-Verilog] PLL_50MHz_to_12MHz

Description: Verilog HDL语言编写EP2C8Q208芯片PLL分频的简单程序，50MHz分频为12MHz-Verilog HDL language，EP2C8Q208 chip， PLL frequency of simple procedures, 50MHz to 12MHz frequency
Platform: | Size: 53248 | Author: LM | Hits:

[VHDL-FPGA-Verilog] PLL

Description: Phase locked loop(PLL) Verilog HDL code
Platform: | Size: 20480 | Author: hr | Hits:
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