Description: 分频电路和包括他的数字PLL电路，能够抑制输出信号的抖动，包括第一电路模块它用输入信号作为第一参考时钟信号，并有分频器确定信号选择的分频率对输入信号进行分频-frequency divider circuit and including his figures PLL circuit, the output signal can inhibit the quiver, including the first circuit module that it is using the input signal as a first reference clock signal. Frequency Divider and determine the choice of signal frequency to input signal frequency Platform: |
Size: 1090492 |
Author:孔嘉 |
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Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift. Platform: |
Size: 1024 |
Author:杨化冰 |
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Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
-Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time. Platform: |
Size: 553984 |
Author:裴雷 |
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Description: DPLL由 鉴相器、 模K加减计数器、脉冲加减电路、同步建立侦察电路、模N分频器构成.
整个系统的中心频率(即signal_in和signal_out的码速率的2倍)为clk/8/N. 模K加减计数器的K值决定DPLL的精度和同步建立时间,K越大,则同步建立时间长,同步精度高.反之则短,低.
-DPLL by the phase detector, K addition and subtraction counter mode, pulse subtraction circuit, synchronous detection circuit established, constitute a model N divider. The whole system of the center frequency (ie signal_in and signal_out the code rate of 2 times) to clk/8/N. modulus K K value addition and subtraction counter DPLL decision to establish the accuracy and synchronization time, K is larger, the simultaneous establishment of a long time, synchronization accuracy. contrary is short and low. Platform: |
Size: 1024 |
Author:鬼舞十七 |
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Description: 数字锁相环频率合成器的设计，数字鉴相器，数字滤波器，数控振荡器，反馈分频器-Digital PLL frequency synthesizer, digital phase detector, digital filter, digital control oscillator, the feedback divider Platform: |
Size: 798720 |
Author:taotao |
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Description: 用verilog语言制作一个PLL，这个PLL可以将频率除频到12MHZ，将PLL除频成12MHZ输出-Verilog language production with a PLL, the PLL frequency divider can be to 12MHZ, 12MHZ into the PLL output divider Platform: |
Size: 55296 |
Author:郑先生 |
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Description: The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group.-The Slow Peripherals Clock Group includes the McBSPs, I2C, and the UART. The input clock to this clock
group is taken the output of divider 2 (D2). by default, the divider is set to divide its input clock by
four, but the divide value can be changed to divide-by-1 or divide-by-2 by modifying the PLLDIV2 bits of
the PLL Divider2 Register (PLLDIV2) through software. The clock frequency of the Slow Peripherals Clock
Group must be equal to or less than that of the Fast Peripherals Clock Group. Platform: |
Size: 4096 |
Author:ehsan |
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Description: 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter shaping filter with FIR, finally get the output. Platform: |
Size: 6779904 |
Author:猪头 |
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Description: 一种设计数字锁相环的思路，包含异或鉴相器、k模可逆计数器、脉冲加减计数器、N分频器等，实现相位的锁定。(A design of digital phase locked loop (PLL) consists of a phase discriminator, a K mode reversible counter, a pulse addition and subtraction counter, a N frequency divider and so on, to lock the phase.) Platform: |
Size: 1024 |
Author:和风5254 |
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