Description: verilog 三分频 分频器是FPGA设计中使用频率非常高的基本设计之一，尽管在目前大部分设计中，广泛使用芯片厂家集成的锁相环资源，如altera 的PLL，Xilinx的DLL.来进行时钟的分频，倍频以及相移。-verilog-third of the frequency divider is a FPGA design, very high frequency of use, one of the basic design, although most of the designs in the current widespread use of factory-integrated PLL chip resources, such as altera of the PLL, Xilinx' s DLL. to for the sub-clock frequency multiplier and phase shift. Platform: |
Size: 1024 |
Author:杨化冰 |
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Description: Cyclone™ FPGA具有锁相环（PLL）和全局时钟网络，提供完整的时钟管理方案。Cyclone PLL具有时钟倍频和分频、相位偏移、可编程占空比和外部时钟输出，进行系统级的时钟管理和偏移控制。Altera® Quartus® II软件无需任何外部器件，就可以启用Cyclone PLL和相关功能。本文将介绍如何设计和使用Cyclone PLL功能。
PLL常用于同步内部器件时钟和外部时钟，使内部工作的时钟频率比外部时钟更高，时钟延迟和时钟偏移最小，减小或调整时钟到输出（TCO）和建立（TSU）时间。
-Cyclone ™ FPGA with a phase-locked loop (PLL) and the global clock network and provide a complete clock management solution. Cyclone PLL with the clock multiplier and divider, phase offset, programmable duty cycle and the external clock output for system-level clock management and offset control. Altera ® Quartus ® II software does not require any external devices, you can enable the Cyclone PLL and related functions. This article describes how to design and use the Cyclone PLL features. PLL clock devices commonly used in the synchronization of internal and external clock, so that the inner workings of the clock frequency higher than the external clock, clock delay and clock skew minimum, reduce or adjust the clock to the output (TCO) and the establishment of (TSU) time. Platform: |
Size: 553984 |
Author:裴雷 |
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Description: 利用VHDL语言对FPGA进行锁相环倍频，经调试已经在开发板上实现倍频-The FPGA using VHDL language PLL frequency multiplier, the debug board has been achieved in the development of frequency Platform: |
Size: 361472 |
Author:huangshaobo |
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Description: 基于EP2C8的锁相环倍频文件 原来时钟为25Mhz 倍频为100Mhz-File the original clock of the EP2C8 the phase locked loop frequency multiplier 25Mhz for 100Mhz Platform: |
Size: 384000 |
Author:Young |
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Description: 本系统是以FPGA（EP2C8Q240C8）为控制核心，由压控振荡器、PLL倍频器、高频功率放大器、遥控器及LCD显示模块组成的压控LC振荡器。能实现输出正弦波频率在15MHZ~35MHZ步进可调，其最小步进为5002HZ，频率稳定度为10-5。当输出信号的频率为30MHZ、峰峰值稳定在1V左右时，在+12V单电源工作的情况下，功率放大器能实现在50Ω纯阻性和50Ω+20pf容性负载上输出功率大于20mw。LCD显示模块能实时显示输出信号的峰峰值和频率，精度由于10 。-This system is based on FPGA ( EP2C8Q240C8 ) as the control core, by a voltage controlled oscillator, PLL multiplier, high frequency power amplifier, remote control and LCD display module comprising a voltage-controlled LC oscillator. Can realize the output sine wave frequency in the step 15MHZ~35MHZ is adjustable, the smallest Bu Jin 5002HZ, frequency stability 10-5. When the frequency of the output signal is 30MHZ, peak stable at about 1V, in+12V single supply situation, the power amplifier can be realized in 50 Ωto 50 Ω+20pf pure resistive and capacitive load on the output power is greater than 20mw. LCD display module can display the output signal and the peak frequency, precision due to 10 . Platform: |
Size: 293888 |
Author:tian |
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Description: FPGA中PLL模块的测试代码，代码通过例化一个PLL将25MHz系统时钟倍频到50MHz，然后通过两个不同频率时钟控制两个LED灯闪烁，通过闪烁频率可用观察PLL倍频效果-The FPGA PLL module test code, the code by instantiating a PLL to 25MHz system clock frequency doubling to 50MHz, and then by two different frequency clock control two LED lights flicker, flicker frequency can be used to observe the PLL multiplier effect Platform: |
Size: 145408 |
Author:wicoboy |
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Description: 基于DSP6713，对DSP内的锁相环相关的寄存器进行设置，实现锁相环倍频功能，DSP入门级资料。-Based on the DSP6713, the DSP phase-locked loops in the relevant register set, realization of PLL frequency multiplier function, DSP entry-level data. Platform: |
Size: 1184768 |
Author:李华 |
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Description: 实现pll分频功能倍频功能可得到fpga说需要的频率实现多的时钟输入-Multiplier pll divide function to achieve functionality available fpga said I need to achieve multi-frequency clock input Platform: |
Size: 3072 |
Author:李安 |
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