Search - processor vhdl code

[VHDL-FPGA-Verilog] core_arm.tar

Description: 用VHDL语言实现的ARM处理器的标准内核的源代码程序，可在重用-use of the VHDL standard ARM processor core source code procedures, the reuse
Platform: | Size: 655360 | Author: 昭君 | Hits:

[VHDL-FPGA-Verilog] Sparc_leon_VHDL

Description: 一个航天航空用的Sparc处理器（配美国欧洲宇航局用的R_tems嵌入式操作系统）的VHDL源代码，但不能保证版图设计ASIC成功 -the Sparc processor (fitted with the United States of the European Space Agency R_tems Embedded operating system) VHDL source code, but it can not guarantee success ASIC Layout
Platform: | Size: 1873920 | Author: 韩红 | Hits:

[MPI] source

Description: MIPS处理器VHDL代码，实现加法，减法乘除等运算，可综合，-MIPS processor VHDL code, realize adder, subtraction multiplication and division and other operations can be integrated,
Platform: | Size: 6144 | Author: 陈丰 | Hits:

[MPI] MIPS

Description: MIPS处理器的顶层VHDL代码，可综合，可仿真，属硬件描述语言，集成电路设计代码-MIPS processor top-level VHDL code can be integrated to simulation, a hardware description language, integrated circuit design code
Platform: | Size: 1024 | Author: 陈丰 | Hits:

[VHDL-FPGA-Verilog] fpu

Description: 使用VHDL语言描述的单精度浮点处理器。源代码来自国外网站。可实现单精度浮点数的加减乘运算。-Described in VHDL language using single-precision floating-point processor. Web site source code from abroad. Can be achieved single precision floating point addition and subtraction, multiplication.
Platform: | Size: 16384 | Author: WeimuMa | Hits:

[VHDL-FPGA-Verilog] LC3-VHDL-another

Description: 另一套LC3 CPU VHDL源码及设计文档，对LC3进行了一些取舍和改造，比如NZP改为NZC，更贴近现实CPU硬件架构。按照ASM进行VHDL编码，更适合数字设计初学者学习。-Another set of LC3 CPU VHDL source code and design documents, of LC3 to a number of trade-offs and transformation, such as NZP changed NZC, more close to reality CPU hardware architecture. In accordance with the ASM to VHDL coding, digital design more suitable for beginners to learn.
Platform: | Size: 808960 | Author: guo | Hits:

[SCSI-ASPI] dlx_verilog

Description: 这是我个人写的DLX处理器流水线的Verilog代码，在ModelSim中仿真通过，并且在ISE中能综合！即可以下载到FPGA中运行指令，指令可以根据需要定义，也可和相应的编译器配合使用，这里给学习流水线和Verilog的朋友共享。-This is my personal wrote DLX pipeline processor Verilog code, adopted in the ModelSim simulation and can be integrated in the ISE! That can be downloaded to the FPGA to run commands, instructions can be defined as needed, but also the compiler and the corresponding use, where to learn lines and Verilog friends sharing.
Platform: | Size: 9216 | Author: 李乔 | Hits:

[Other] ARM_and_Verilog

Description: arm处理器的vhdl源代码编写，可以参考-arm processor VHDL source code to prepare, can refer to
Platform: | Size: 3226624 | Author: 黄伟 | Hits:

[VHDL-FPGA-Verilog] code

Description: 一个8位微处理器的VHDL代码以及testbench-8-bit processor VHDL
Platform: | Size: 8192 | Author: fei | Hits:

[Editor] processor.tar

Description: i need of vhdl code for 32-bit risc processor
Platform: | Size: 48128 | Author: ganesh | Hits:

[VHDL-FPGA-Verilog] 87361039

Description: 于一个8位处理器的分析，和源代码，VHDL语言设计，经过测试-An 8-bit processor in the analysis, and source code, VHDL language design and tested
Platform: | Size: 92160 | Author: hbei | Hits:

[VHDL-FPGA-Verilog] KM

Description: vhdl code 16 bit processor
Platform: | Size: 10240 | Author: kante | Hits:

[Software Engineering] mnl_nios_programmers32

Description: nios处理器的介绍以及汇编代码的说明，altera公司的官方文件-introduction of nios processor & description of assembly code
Platform: | Size: 1100800 | Author: 丁丁 | Hits:

[Other] MANIK

Description: MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).-MANIK is a 32 bit RISC Microprocessor. The salient features of the processor are listed below. Features Hardware Features • Data Path Width 32 bits, with Four stage pipeline. • Mixed 16/32 bit instructions for code density • Von Neumann Architecture (Data and Instruction in the same address space). • Sixteen, 32 bit General Purpose Registers. • Four USER defined instructions (with Register File Write back capability).
Platform: | Size: 3395584 | Author: hfayed | Hits:

[Other] P7_Procesador

Description: SIMPLE PROCESSOR CODE
Platform: | Size: 1303552 | Author: anaterremoto | Hits:

[matlab] dlx.tar

Description: these is about code for dlx processor
Platform: | Size: 36864 | Author: satyanarayana | Hits:

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