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[Other resource] S3Demo

Description: 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS / 2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Platform: | Size: 292348 | Author: 计算机 | Hits:

[VHDL-FPGA-Verilog] S3Demo

Description: 用FPGA模拟VGA时序、模拟PS/2总线的键盘接口VHDL源代码，基于Xilinx spartan3-VGA FPGA timing simulation, simulation PS/2 keyboard interface bus VHDL source code, Based on Xilinx spartan3
Platform: | Size: 291840 | Author: 计算机 | Hits:

[VHDL-FPGA-Verilog] mouse_control

Description: 1、 用FPGA实现PS/2鼠标接口。 2、 鼠标左键按下时十字形鼠标图象的中间方块改变颜色，右按下时箭头改变颜色。 3、 Reset按键：总复位。 -one with FPGA PS/2 mouse interface. 2, the left mouse button pressed cruciform images in the middle mouse to change the color box, press the right arrow at the change in color. 3, Reset buttons : the total reduction.
Platform: | Size: 9216 | Author: lee | Hits:

[Embeded-SCM Develop] EXPT12_11_Ps2Key

Description: 基于fpga和sopc的用VHDL语言编写的EDA的PS/2鼠标键盘控制模块-FPGA and SOPC based on the use of VHDL language EDA s PS/2 mouse keyboard control module
Platform: | Size: 33792 | Author: 多幅撒 | Hits:

[Embeded-SCM Develop] EXPT12_12_VGAgame

Description: 基于fpga和sopc的用VHDL语言编写的EDA的PS/2鼠标与VGA控制模块-FPGA and SOPC based on the use of VHDL language EDA s PS/2 mouse and VGA control module
Platform: | Size: 29696 | Author: 多幅撒 | Hits:

[Embeded-SCM Develop] EP1C6_12_12_VGAgame

Description: 基于fpga和sopc的用VHDL语言编写的EDA的PS/2和VGA控制显示控制器-FPGA and SOPC based on the use of VHDL language EDA s PS/2 and VGA display controller to control
Platform: | Size: 27648 | Author: 多幅撒 | Hits:

[Embeded-SCM Develop] cfg_cyclone_fpga

Description: 采用CPLD来培植ALTERA公司的CYCLONE系列FPGA，（AS，PS，FAS）可选-CPLD used to cultivate ALTERA company CYCLONE series FPGA, (AS, PS, FAS) optional
Platform: | Size: 13312 | Author: 梁光辉 | Hits:

[Embeded-SCM Develop] USRP_REV_4_2

Description: 软件无线电USRP v4.2版本硬件原理图，包括clock、debug board、fpga、interface、power等部分，有pdf、sch、ps等多种格式。-Software Radio USRP v4.2 version of the hardware schematic diagram, including clock, debug board, fpga, interface, power and other parts, there are pdf, sch, ps, such as a variety of formats.
Platform: | Size: 1079296 | Author: wivy | Hits:

[VHDL-FPGA-Verilog] altera_up_avalon_ps2

Description: 花了半个月才改好的Atera DE1/DE2 ps2 IP 驱动核。放在FPGA工程目录下可以直接使用。本IP能够驱动PS/2键盘和鼠标。使用时只要调用HAL目录下的文件即可以直接使用！-Spent a good two weeks we have made some changes Atera DE1/DE2 ps2 IP-driven nuclear. On the FPGA project directory can be used directly. The IP to drive PS/2 keyboard and mouse. When used as long as the call HAL directory file that can be used directly!
Platform: | Size: 27648 | Author: 王乔 | Hits:

[Software Engineering] ps2_ipcore_design

Description: 电子测量技术 ELECTR0NIC MEASI瓜EMENT TECHN0L0GY 第29卷第3期 2006年6月 PS／2设备接口IP核设计 王 豪黄启俊常 胜 (武汉大学物理学院微电子与固体电子学实验室武汉430072) 摘要：用Verilog硬件描述语言实现了PS／2设备接口的II)核设计，详细描述了II)核的结构划分和各模块的 设计思想，并在FPGA上进行验证。结果表明此 核功能正确，可以方便地在SOPC系统中复用。-Electronic Measurement Technology ELECTR0NIC MEASI melon EMENT TECHN0L0GY Vol 29 No. 3 June 2006 PS/2 device interface IP core design黄启俊Changsheng WANG Hao (School of Physics, Wuhan University Microelectronics and Solid State Electronics Laboratory, Wuhan 430072) Abstract: Verilog hardware description language to achieve a PS/2 device interface of II) of nuclear design, described in detail II) the structure of nuclear division and the module
Platform: | Size: 126976 | Author: Morgan | Hits:

[VHDL-FPGA-Verilog] LPT

Description: 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据 自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。-The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
Platform: | Size: 2048 | Author: tianrongcai | Hits:

[VHDL-FPGA-Verilog] ps2

Description: 基于Xilinx Spartan3E的ps/2键盘接口，能够把键值传送到FPGA上并在LCD上显示-Xilinx Spartan3E based on the ps/2 keyboard interface, be able to send to the FPGA on the keys and LCD display
Platform: | Size: 506880 | Author: darkblue | Hits:

[VHDL-FPGA-Verilog] ps2interface

Description: this a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .-this is a fpga sparttan 3e based project in which i have made a game based on vga interface . this file is the supporting file for ps/2 interface .
Platform: | Size: 5120 | Author: yasir | Hits:

[Other] MOUSE_DETECTION

Description: read mouse PS/2 with FPGA
Platform: | Size: 52224 | Author: bayu | Hits:

[VHDL-FPGA-Verilog] AlteraFPGA

Description: FPGA配置,CPS4,AS MODE,PS MODE, JTAG MODE -FPGA config
Platform: | Size: 158720 | Author: 陈澄 | Hits:

[VHDL-FPGA-Verilog] Altera_UP_PS2

Description: Altas default hardware files for PS/2 connection between FPGA and the host(device).
Platform: | Size: 9216 | Author: Dean | Hits:

[VHDL-FPGA-Verilog] clock

Description: 一个简单的FPGA时钟，里面有PDF说明~-A simple clock sample. There exists a PDF statement files in it. If there exists any problem please contact me.
Platform: | Size: 21504 | Author: chobits | Hits:

[Other] FPGA-Configuration-AS-PS-JTAG

Description: 相信很多初学FPGA的朋友们对FPGA的几种配置模式（JTAG PS AS）都是模棱两可、云里雾里的。本文详细地介绍了几种配置模式，对FPGA初学者有很好的帮助。-I believe that a lot of novice FPGA friends on several of the FPGA configuration mode (JTAG PS AS) are ambiguous and foggy. This paper describes several configuration mode, the FPGA beginners have a good help.
Platform: | Size: 8192 | Author: 东方泓 | Hits:

[VHDL-FPGA-Verilog] zcu102_exp_1

Description: 给予Xilinx系列zcu102开发板，完成了一个基本的project，实现了PS 端对PL 端的控制，并在PL端自己生成IP，是初学者很好的学习模板。(Xilinx series zcu102 development board, completed a basic project, the PS end to the PL control, and the PL end of the generation of IP, is a good learning template for beginners.)
Platform: | Size: 27393024 | Author: ICwxforever | Hits:

[VHDL-FPGA-Verilog] A4_Mod_Top

Description: 多终端点歌系统实验，我们可以使用串口外设发送0~9这10个数字控制蜂鸣器发出不同的音调，可以使用PS/2外设发送0~9这10个数字控制蜂鸣器发出不同的音调，还可以使用红外外设发送0~9这10个数字控制蜂鸣器发出不同的音调。(Multi terminal point song system experiment, we can use the serial port peripherals to send 0~9 10 numbers to control the buzzer to send different tones, can use PS/2 peripherals to send 0~9 the 10 numbers to control the buzzer to send different tones, and can use the infrared peripherals to send the 10 digital words to control the buzzer to send different tones.)
Platform: | Size: 4118528 | Author: 健伟 | Hits:
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