Search - quartus cpu

[VHDL-FPGA-Verilog] risc cpu

Description: 一个很好的16位cpu ip内核，用quartus写的
Platform: | Size: 5888 | Author: kingkoyan | Hits:

Description: Quartus II 5.0下写的一个单总线架构的CPU设计，包括控制器、运算器、译码电路等。模拟的时钟脉冲也给出。已经通过Quartus II 5.0运行。可以给需要设计总线架构CPU的同学一点参考。-Quartus II 5.0 written under a single bus architecture of the CPU design, including controllers, computing devices, such as decoding circuitry. Simulated clock pulse is also given. Has been run through the Quartus II 5.0. Can be addressed to the need to design bus architecture students CPU reference point.
Platform: | Size: 800768 | Author: 陈佳 | Hits:

[VHDL-FPGA-Verilog] risc_cpu

Description: 8位risc cpu的编写，使用quartus软件对其进行写入，里面内置乘法器、除法器等模块-8-bit risc cpu the preparation, use the Quartus software to write, which built-in multiplier, divider modules
Platform: | Size: 814080 | Author: 瑞翔 | Hits:

[VHDL-FPGA-Verilog] niosII_system_cpu

Description: cpu代码，可在ISE或quartus下完成调试-cpu code, can be accomplished under the ISE or Quartus debugging
Platform: | Size: 12288 | Author: | Hits:

[VHDL-FPGA-Verilog] ALU

Description: vhdl代码使用quartus编译 cpu中 alu的设计可作为课程设计的参考此为16的运算器-VHDL code using Quartus compiler cpu in alu design of curriculum design can be used as a reference for this for 16 computing device
Platform: | Size: 1024 | Author: 闵瑞鑫 | Hits:

[Other Embeded program] LCD

Description: Quartus, Sopc Builder搭建的CPU，通过NIOS控制LCD。工程文件。-Quartus, Sopc Builder to build the CPU, through the NIOS control LCD. Engineering documents.
Platform: | Size: 2997248 | Author: 小杨 | Hits:

[Linux-Unix] CPU8051V1

Description: 可用的CPU8051，已经多个项目验证，希望更多的朋友使用它开放！-CPU8051
Platform: | Size: 86016 | Author: 凌朝东 | Hits:

[ARM-PowerPC-ColdFire-MIPS] pipeline

Description: 用Quartus II 设计的3级流水CPU，指令采用二次重叠执行方式-Quartus II design with three-stage pipeline CPU, instruction execution overlaps with the second time
Platform: | Size: 3028992 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] Microprogramcontroller

Description: 微程序控制器部件实验，使用VHDL语言使用Quartus测试通过，模拟CPU-Micro-program controller component experiments, the use of VHDL language use Quartus test, simulation CPU
Platform: | Size: 752640 | Author: 糖糖 | Hits:

[VHDL-FPGA-Verilog] mips

Description: MIPs CPU，VERILOG代码，经过QUARTUS综合，时序分析，验证无误。-MIPS CPU
Platform: | Size: 5120 | Author: 王龙 | Hits:

[Other] PipelineCPU

Description: Quartus II 7.2环境中，采用硬件描述语言VHDL独立完成了基于MIPS指令集的32位RISC处理器的逻辑设计-quartusII mips pipeline 32bit cpu design
Platform: | Size: 847872 | Author: znl | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个完整的流水CPU设计，quartus平台，Verilog实现-CPU design a complete water, quartus platform, Verilog realization
Platform: | Size: 1100800 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 一个多周期CPU的完整设计，quartus平台，Verilog实现，内含实验报告，和详细的各模块功能表-Complete a multi-cycle CPU design, quartus platform, Verilog implementation, includes lab reports, and a detailed menu of each module
Platform: | Size: 6606848 | Author: 涯 | Hits:

[VHDL-FPGA-Verilog] danzhouqiCPU

Description: VHDL单周期CPU设计,基于Quartus II 开发平台-VHDL single-cycle CPU design, Quartus II development platform based on
Platform: | Size: 1587200 | Author: 逆天之刃 | Hits:

[VHDL-FPGA-Verilog] cpu

Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
Platform: | Size: 931840 | Author: 姜涛 | Hits:

[VHDL-FPGA-Verilog] CPU

Description: 这是用Quartus II 6.0做的CPU实验，是计算机组成原理专题实验。-This is done using Quartus II 6.0 CPU experiment, experimental feature is the computer organization.
Platform: | Size: 309248 | Author: wangbluer | Hits:

[Other] CPU

Description: 武汉大学计算机组成原理综合实验 quartus cpu 模型-Wuhan University, Computer Organization Model of Integrated Experiment quartus cpu
Platform: | Size: 902144 | Author: AA | Hits:

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[VHDL-FPGA-Verilog] risc cpu

[Software Engineering] mycpu

[VHDL-FPGA-Verilog] risc_cpu

[VHDL-FPGA-Verilog] niosII_system_cpu

[VHDL-FPGA-Verilog] ALU

[Other Embeded program] LCD

[Linux-Unix] CPU8051V1

[ARM-PowerPC-ColdFire-MIPS] pipeline

[VHDL-FPGA-Verilog] Microprogramcontroller

[VHDL-FPGA-Verilog] mips

[Other] PipelineCPU

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] danzhouqiCPU

[VHDL-FPGA-Verilog] cpu

[VHDL-FPGA-Verilog] CPU

[Other] CPU

[VHDL-FPGA-Verilog] cu

[VHDL-FPGA-Verilog] CPU

[VHDL-FPGA-Verilog] cpu

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