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Description: Nios系统, 加入了VGA控制器和USB鼠标控制器-Nios system, add a VGA controller and the USB mouse controller
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Size: 909312 |
Author: |
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Description: 通过VHDL实现4位全加器，8位全加器，和8位通用寄存器的设计-4-bit full adder
8-bit full adder
8-bit register
using vhdl
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Size: 924672 |
Author: yepp_u2 |
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Description: Quartus II was a development tool of CPLD / FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer / Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis-Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
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Size: 202752 |
Author: jay |
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Description: 一个简单的CPU设计，支持add，sub，mvi，mv四条指令，用Verilog语言编写，在Quratus II上编译通过，仿真正确。-A simple CPU design, support add, sub, mvi, mv four instructions, with the Verilog language, compiled by the Quratus II, the simulation is correct.
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Size: 931840 |
Author: 姜涛 |
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Description: 使用ModelSim对Altera设计进行时序仿真的简要操作步骤 1.建立工程，设置仿真工具选项参数
2.使用Quartus II编译工程
3.建立仿真工程
4.Altera仿真库的编译与映射
5.编译HDL源代码和Testbench
6.启动仿真器并加载设计顶层
7.打开观测窗口，添加信号
8.执行仿真-Using ModelSim Altera design for timing simulation of brief steps 1. Establish project simulation tool options set parameters
2. Use the Quartus II compilation project
3. Establish simulation project
Compilation and mapping 4.Altera emulation library
5. Compile HDL source code and Testbench
6. Start the emulator and the top load design
7. Open the observation window, add signals
8. perform simulation
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Size: 2948096 |
Author: 朱潮勇 |
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