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[Other Embeded program] QuartusII_RAM

Description: 介绍了QUARTUSII中ram的应用，以及基于它的NIOS嵌入式小系统设计-were introduced QUARTUSII ram applications, and based on its small Nios Embedded System Design
Platform: | Size: 307200 | Author: 黎明 | Hits:

[MiddleWare] MIF_create

Description: MIF文件生成器 用于quartus II等软件的ROM表mif文件生成-MIF file generator quartus II software for the ROM table to generate mif file
Platform: | Size: 221184 | Author: 高 | Hits:

[VHDL-FPGA-Verilog] ram_256

Description: 在Quartus中实现256的RAM，经过实际的应用验证，没有问题的-Quartus achieved in 256 of the RAM, through the practical application of verification, no problem
Platform: | Size: 145408 | Author: 郭翠双 | Hits:

[Embeded-SCM Develop] quartus

Description:
Platform: | Size: 10531840 | Author: liuhongjie | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] tut_nios2_introduction

Description: This tutorial presents an introduction to Altera’s Nios R II processor, which is a soft processor that can be in- stantiated on an Altera FPGA device. It describes the basic architecture of Nios II and its instruction set. The NiosII processor and its associated memory and peripheral components are easily instantiated by using Altera’s SOPCBuilder in conjuction with the Quartus R II software.
Platform: | Size: 116736 | Author: *Roma* | Hits:

[VHDL-FPGA-Verilog] lpm_ram

Description: 一个基于quartus的LPM_RAM例子，VHDL语言写的，通过仿真测试-Quartus the LPM_RAM based on examples, VHDL language, and through simulation testing
Platform: | Size: 221184 | Author: a64577122 | Hits:

[Books] Crack_QII90

Description: 您现在阅读的是 Quartus II 简介手册。 Altera® Quartus® II 设计软件是适合 单芯片可编程系统 (SOPC) 的最全面的设计环境。 如果您以前用过 MAX+PLUS® II 软件、其它设计软件或 ASIC 设计软件，并且准备改用 Quartus II 软件，或如果您对 Quartus II 软件有了一些了解但想进一步了解 它的功能，那么本手册非常适合您。-You are reading the Quartus II brochure. Altera ® Quartus ® II design software is suitable for Single-Chip Programmable System (SOPC) the most comprehensive design environment. If you ve used MAX+ PLUS ® II software, ASIC design software or other design software, and is prepared to use Quartus II software, or if you have some understanding of Quartus II software, but would like to learn more about Its function, then this manual is for you.
Platform: | Size: 29696 | Author: 陈冉 | Hits:

[VHDL-FPGA-Verilog] Quartus_CRACK

Description: Quartus_CRACK_license.dat破解文件，对初学软件的朋友有用。-Quartus_CRACK_license.dat crack file, be useful for beginners software friends.
Platform: | Size: 315392 | Author: WANG | Hits:

[VHDL-FPGA-Verilog] tut_signaltapII_verilogDE2

Description: Altera公司原版设计手册，关于signaltap ii。-This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implementation in Altera’s FPGAs.
Platform: | Size: 380928 | Author: Han Yunbo | Hits:

[VHDL-FPGA-Verilog] signaltapII_verilogDE2

Description: This tutorial explains how to use the SignalTap II feature within Altera’s Quartus R II software. The Signal- Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implementation in Altera’s FPGAs.-This tutorial explains how to use the SignalTap II feature within Altera' s Quartus R II software. The Signal-Tap II Embedded Logic Analyzer is a system-level debugging tool that captures and displays signals in circuits designed for implementation in Altera' s FPGAs.
Platform: | Size: 380928 | Author: hejianlun | Hits:

[VHDL-FPGA-Verilog] spi

Description: SPI总线接口的verilog源码，包含仿真模块modelsim 和 quartus 工程。本人测试通过。-SPI bus interface in verilog source code, including the simulation module modelsim and quartus project. I test.
Platform: | Size: 290816 | Author: 阿虎 | Hits:

[Software Engineering] 1tut_quartus_intro_schem

Description: 图解介绍Quartus II Design。主要介绍了我国QuartusR II CAD系统。-Quartus II Introduction Using Schematic Design。This tutorial presents an introduction to the Quartus R II CAD system.
Platform: | Size: 824320 | Author: Laura Ku | Hits:

[VHDL-FPGA-Verilog] DE2_TV

Description: 本代码为Altera DE2开发板例程源码，（FPGA：EP2C35F672C6）quartus II 9.0以上可以编译（随板源码为7.2以下版本，在9.0以上版本编译会报错）。本代码实现一个音视频播放器TV_BOX。-This demonstration plays video and audio input a DVD player using the VGA output and audio CODEC on the DE2 board. There are two major blocks in the circuit, called I2C_AV_Config and TV_to_VGA. The TV_to_VGA block consists of the ITU-R 656 Decoder, SDRAM Frame Buffer, YUV422 to YUV444, YCrCb to RGB, and VGA Controller.
Platform: | Size: 215040 | Author: chenxin | Hits:

[VHDL-FPGA-Verilog] LCD

Description: LCD的循环输出，在Quartus二的环境下进行开发，DE2-70的开发板，用VHDL语言编写-LCD de xúnhuán shūchū, zài Quartus èr de huánjìng xià jìnxíng kāifā,DE2-70 de kāifā bǎn, yòng VHDL yǔyán biānxiě
Platform: | Size: 627712 | Author: 王鲁苏 | Hits:

[VHDL-FPGA-Verilog] test3

Description: 本实验的任务就是利用 Quartus II 软件的文本输入，产生一个基本触发器， 触发器的形式可以是与非门结构的，也是可以或非门结构的。实验中用按键模块 的用键 7 和键 8 来分别表示 R 和 S，用 LED 模块的 LED D1 和 LED D2 分别表示 Q 和Q 。在 R 和 S 满足式（ 2）的情况下，观察 Q 和Q 的变化。-The experiment task is to use Quartus II software, text input, generates a basic flip-flop, flip-flop may be a form, you can also structure NAND gate NOR gate structure. Use the key experiment using key module 7 and 8 keys to represent the R and S, with LED D1 and LED D2 LED module respectively Q and Q. In the case of R and S satisfy the formula (2) under observation Q and Q change.
Platform: | Size: 228352 | Author: 小方 | Hits:

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