Description: 用vhdl语言编写的基于fpga的波形发生器,使用了quartusII程序。可以在1602液晶显示器上显示目前的波形种类。产生的波形分别是正弦波,三角波,锯齿波和方波。-VHDL language using FPGA-based waveform generator, using the procedures quartusII. 1602 liquid crystal display can show the current waveform types. Generated waveforms are sine wave, triangle wave, sawtooth and square wave. Platform: |
Size: 1708032 |
Author:zhg |
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Description: Quartus开发环境下开发的Arinc 429总线收发器工程,由于产权问题,提供的程序有删减,标号未尽规范。-Quartus development environment developed under the Arinc 429 bus transceiver works, because the issue of property rights, provided procedures are deleted, not standardized labeling. Platform: |
Size: 679936 |
Author:wangyunshann |
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Description: 基于QUARTUSII软件 实现FPGA(ATERA CYCLONE II系列)与SD卡SD模式通信
所用语言位verilog HDL-QUARTUSII software implementation based on FPGA (ATERA CYCLONE II series) with SD Card SD mode digital communication language verilog HDL Platform: |
Size: 5064704 |
Author:chenbinjie |
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Description: VHDL教程 ppt版
绪论
第一章 VHDL基本结构
第二章 VHDL语言元素
第三章 VHDL的描述风格
第四章 VHDL的主要描述语句
第五章 组合逻辑电路设计
第六章 时序逻辑电路设计-Ppt version of VHDL Tutorial VHDL Introduction Chapter I Chapter II the basic structure of VHDL language element of VHDL in Chapter III Chapter IV describes the style of the main description language VHDL Chapter V combinational logic circuit design of Chapter VI of sequential logic circuit design Platform: |
Size: 1081344 |
Author:陈松 |
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Description: 本设计根据OFDM系统的实际需要,提出一种用FPGA实现FFT运算的方案,并以64点FFT为例,在Quartus II软件上通过了综合和仿真。-The design of OFDM systems in accordance with the actual needs of a computing using FPGA realize FFT program, and 64-point FFT as an example, in the Quartus II software through a comprehensive and simulation. Platform: |
Size: 27648 |
Author:叶开 |
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Description: FPGA开发入门的Verilog HDL程序---流水灯,真实可用,验证通过,工程环境为Altera Quartus -FPGA development of Verilog HDL entry procedures- water lights, the real available, authentication is passed, the project environment for Altera Quartus Platform: |
Size: 193536 |
Author:renyong0801 |
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Description: FPGA设计软件的绝佳入门书籍,本人珍藏,全部吐血奉献之2,请大家赶紧下!-FPGA design software, an excellent entry-books, I treasure all the blood sacrifice of 2, please hurry under the U.S.! Platform: |
Size: 844800 |
Author:beckham |
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Description: 我用VHDL写的正弦,用FPGA内部ROM,有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates Platform: |
Size: 651264 |
Author:jimmy |
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Description: Code was successfully implemented within ALtera FPGA with Quartus 6.0. It presents two polish own female names: ULA and ALA whose are scrolling on the 4-columns crystal LED. When you press the switch it will turn from ULA into ALA and continue scrolling. Platform: |
Size: 1024 |
Author:Gooreck |
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Description: 实现低通采样功能的vhdl代码,可在quartus里运行。-The achievement of low-pass function vhdl sample code can be run in quartus. Platform: |
Size: 4096 |
Author:桑 |
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Description: 基于FPGA的移相式DDS正弦信号发生器的VHDL源代码,压缩包里是在Quartus里做的工程,FPGA用的是Cyclone1C3系列-FPGA-based phase-shifting of the DDS signal generator sine VHDL source code, compressed in the bag is done in Quartus Engineering, FPGA is used Cyclone1C3 Series Platform: |
Size: 49152 |
Author:deadtomb |
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Description: 基于FPGA的数字存储示波器,用VHDL实现的,压缩包里是Quartus工程。AD采样送进FPGA,存入SRAM后用DA在普通示波器上可以显示。-FPGA-based digital storage oscilloscope, using VHDL achieved compression is Quartus project bag. AD sample into FPGA, after SRAM into DA in ordinary oscilloscope can display. Platform: |
Size: 61440 |
Author:deadtomb |
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Description: Quartus II工程压缩文件,是一个典型的基于FPGA的秒表工程项目,有50MHz分频、计数、译码等模块。采用VHDL语言编写。-Quartus II project files, is a typical FPGA-based project of the stopwatch, a 50MHz frequency, counting, decoding modules. Using VHDL language. Platform: |
Size: 464896 |
Author:kg21kg |
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Description: 教你在Quartus II中如何实用LPM库,对与FPGA系统设计有很好指导作用-Teach you how to Quartus II in the LPM utility library, with the FPGA system design have a very good guide Platform: |
Size: 352256 |
Author:钟桂东 |
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Description: 用verilog 语言写的FPGA子程序,环境是quartus II 7.2 已经在EP1C6Q240上测试过,源码包含仿真文件和仿真结果,本程序可以直接嵌入做子程序使用。-FPGA with the verilog language written subroutines, the environment is quartus II 7.2 has been tested on EP1C6Q240, source code contains the simulation files and simulation results, this procedure can be embedded directly used to do routines. Platform: |
Size: 1163264 |
Author:黄家武 |
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