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[Other resource] NRS4000_cpu

Description: 现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、Cache等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ＲＯＭ以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明，这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length.
Platform: | Size: 41303 | Author: chengp | Hits:

[Driver Develop] DDK_BCHKD_Custom_Events

Description: RAM Disk Driver with custom BoundsChecker events This sample illustrates how to add custom BoundsChecker events to a DDK driver. It links to the kchecker library and has several BOUNDSCHECKER() calls in it. This sample is a software only Windows NT Device Driver. This driver is provided for educational purposes only. Generally the Windows NT cache manager does a much better job of optimizing memory usage than using a RAM disk.-RAM Disk Driver with custom BoundsChecker events This sample illustrates how to add custo m BoundsChecker events to a DDK driver. It links kchecker to the library and has several BOUNDSC HECKER () calls in it. This sample is a software o nly Windows NT Device Driver. This driver is pro vided for educational purposes only. Generall y the Windows NT cache manager does a much better job of optimizing memory usage than using a RAM d isk.
Platform: | Size: 23593 | Author: wiyn | Hits:

[Other] C8051F120中文数据手册

Description:

C8051F单片机是目前最快的单片机，兼容C51，压缩包里是中文手册，对编程有帮助。

C8051F120是完全集成的混合信号系统级MCU芯片。下面列举了一些主要芯片资源：
·高速流水线结构的8051兼容的CIP-51内核，使用内部集成 PLL时速度可达 100MIPS；2 周期16 x 16 MAC引擎，指令数据高速缓存操作(Cache)；
·全速非侵入式的系统调试接口（片内）；
·真正12位100ksps的8通道ADC，带PGA和模拟多路开关；8位500ksps的8通道ADC；
·两个12位DAC，可编程更新时序；
·128K字节可在系统编程的FLASH存储器；
·8448字节内部数据 RAM（8K + 256）；
·可寻址64K字节地址空间的外部数据存储器接口；
·硬件实现的SPI，SMBus/IIC和两个UART串行接口；
·5个通用的16位定时器；
·具有6个捕捉/比较模块的可编程计数器/定时器阵列；
·片内看门狗定时器，2个比较器，VDD监视器和温度传感器；
·64个I/O端口；
·-40~85度工业级温度范围；
·2.7V~3.6V工作电压，100脚TQFP封装；
 


Platform: | Size: 3754840 | Author: changlian | Hits:

[Industry research] NRS4000_cpu

Description: 现代先进微处理器有非常高的集成度和复杂度，又有寄存器堆、Cache等嵌入式部件，而且芯片管脚数相对较少，必须要有一定的自测试设计和其它的可测试性设计来简化测试代码，提高故障覆盖率。本文简要讨论NRS4000微处理器芯片的以边界扫描测试为主体，以自测试为补充的可测试性设计框架。着重介绍芯片的边界扫描设计和芯片中译码控制器PLA和微程序ＲＯＭ以及采用内嵌RAM结构的指令Cache和寄存器堆的内建自测试设计。仿真结果表明，这些可测试性设计大大缩短了测试代码的长度。-modern microprocessors have a very high degree of integration and complexity, there Register pile, Cache such as embedded components, but Chip few relatively small, There must be the self-test design and testing of other design code to simplify testing, fault coverage. This paper briefly discussed Key words microprocessor chip to the boundary-scan test as the mainstay, Since the test to add to the test design framework. Highlighting the boundary-scan chip design and chip decoder PLA and micro-controller procedures and the use of embedded ROM RA M structure of the instruction cache and register stack of built-in self-test design. The simulation results show that these tests can greatly shorten the design of the test code length.
Platform: | Size: 40960 | Author: chengp | Hits:

[Driver Develop] DDK_BCHKD_Custom_Events

Description: RAM Disk Driver with custom BoundsChecker events This sample illustrates how to add custom BoundsChecker events to a DDK driver. It links to the kchecker library and has several BOUNDSCHECKER() calls in it. This sample is a software only Windows NT Device Driver. This driver is provided for educational purposes only. Generally the Windows NT cache manager does a much better job of optimizing memory usage than using a RAM disk.-RAM Disk Driver with custom BoundsChecker events This sample illustrates how to add custo m BoundsChecker events to a DDK driver. It links kchecker to the library and has several BOUNDSC HECKER () calls in it. This sample is a software o nly Windows NT Device Driver. This driver is pro vided for educational purposes only. Generall y the Windows NT cache manager does a much better job of optimizing memory usage than using a RAM d isk.
Platform: | Size: 23552 | Author: wiyn | Hits:

[SCM] Flash

Description: 不开销缓存RAM的430Flash读写程序-Do not spend the 430Flash cache RAM read and write procedures
Platform: | Size: 1024 | Author: 米凯 | Hits:

[OS Develop] fat16

Description: 完成了一套基于FAT16，并只支持短路径名的函数包。 可用于虚拟磁盘建立。甚至你自己写操作系统，文件系统就可以直接使用他。 由于当初是为朋友在他的板子上跑，只有1K ram,还不能全用，最多只有600-700字节可使用， 所以没有采用缓存的形式，直接采用读写操作。 他可以很轻易的扩充到FAT32（甚至FAT12都可以给予支持），当然还只是支持短路径名。说实在 除了高级应用FAT系列的长文件名真是费事。 这里，我打算将其做成SpaceC的控件之一，用于整合资源文件。-Based on the completion of a set of FAT16, and only supports a short path name of the function package. Can be used for the establishment of a virtual disk. Or even write your own operating system, file system can be directly used on him. Because it was for a friend in his board on the run, only 1K ram, also should not use the whole, a maximum of only 600-700 bytes can be used, there is no form of the use of the cache, directly read and write operations. He can be easily expanded to FAT32 (or FAT12 can support), of course, only to support the short path name. To tell the truth, apart from advanced applications FAT series of long file name is really cumbersome. Here, I intend to make one of SpaceC control for integrated resource file.
Platform: | Size: 19456 | Author: 李卓吾 | Hits:

[Driver Develop] RAMDISK

Description: Ramdisk 是一个用于演示纯软件的 Windows(r) 2000 设备驱动程序的示例。此驱动程序会创建一个指定大小的 RAM 盘。您可以像使用任何其他磁盘一样使用此 Ramdisk，但在您关闭计算机时该磁盘的内容会丢失。（一般来说，Windows(r) 2000 缓存管理器在优化内存使用方面比 Ramdisk 要好得多。）-Ramdisk is a pure software used for demonstration of Windows (r) 2000 device driver sample. This driver creates a RAM disk of specified sizes. You can use any other disk as the same as using the Ramdisk, but when you shut down your computer the contents of the disk will be lost. (Generally speaking, Windows (r) 2000 cache management in optimizing the memory usage much better than Ramdisk.)
Platform: | Size: 24576 | Author: tony zhao | Hits:

[Disk Tools] COMBI-Disk

Description: 一款DOS下的RAM disk和disk cache组合在一起的工具。-A RAM disk under DOS and disk cache combination tool.
Platform: | Size: 38912 | Author: 李政 | Hits:

[Other Embeded program] LCD

Description: 环境 keil 利用c51F 中断刷新 LCD (128*64) 内部ram做显示缓存-Keil the use of environmental disruption c51F refresh LCD (128* 64) do show that the internal ram cache
Platform: | Size: 47104 | Author: LCQ | Hits:

[source in ebook] CodeOptimizationEffectiveMemoryUsage

Description: 《代码优化：有效使用内存》，Kris Kaspersky著，谈明金译，电子工业出版社。本书主要包括以下部分：程序剖分、RAM子系统、高速缓存子系统、及其优化。里面包括了每部分的代码。-" Code Optimization: Effective use of memory" , Kris Kaspersky, and on the prescribed payment translation, Publishing House of Electronics Industry. The book includes the following main parts: the procedure partition, RAM subsystem, cache subsystem, and optimization. Which includes every part of the code.
Platform: | Size: 23117824 | Author: 小明 | Hits:

[Other] dmyh-yxshnc

Description: 本书系统深入地介绍了各种代码优化编程技术。全书分为4章。第1章集中介绍如何确定程序中消耗CPU时钟最多的热点代码的所谓程序剖析技术以及典型部分工具的实用知识。第2，3章分别全面介绍RAM了系统与高速缓存子系统的代码优化知识。第4章主要介绍了机器代码优化技术。各章在讨论基本原理的同时详细给出了代码实例，并对优化性能进行了定量的分析。该书特别适合于作为应用程序员及系统程序员的学习与开发之用。同时，本书对在硬件方面的专业人员与技术工作者有一定的参考价值。-This book system, in-depth description of the various code optimization programming. The book is divided into four chapters. Chapter 1 focus on how to determine the program consumes CPU clock up to the so-called hot code analysis techniques and procedures for a typical part of the tools and practical knowledge. Separately in Chapter 2,3 introduced the first comprehensive system RAM and high-speed cache memory subsystem, the code and optimize their knowledge. Chapter 4 focuses on the machine code optimization techniques. In discussing the various chapters, while the basic principles of the code examples are given in detail, and optimize the performance of the quantitative analysis. Book is particularly suitable as an application programmer and system programmer learning and development purposes. At the same time, this book in terms of hardware professionals and technical workers have a certain reference value.
Platform: | Size: 33901568 | Author: Codeloader | Hits:

[Other] jj

Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
Platform: | Size: 546816 | Author: 黄奇家 | Hits:

[SCM] CCNA8

Description: bootstrap:存储在ROM中的微码(microcode)中,用来在初始化的时候启动router,然后加载IOS 　　POST:存储在ROM中的微码中,用来检查硬件基本配置是否正常,然后决定哪些接口可用 　　ROM monitor:存储在ROM中的微码中,作用是测试和排疑等 Mini-IOS:Cisco叫它RXBOOT或bootloader,它是存储在ROM中的,IOS的简化版本,用来把IOS加载到闪存中 　　RAM(random-access memory):用来保存数据包缓存,ARP缓存,路由表,和running-config配置文件.某些router上,IOS可以从RAM中运行 -bootstrap: stored in the ROM of the micro-code (microcode) in the time used to initialize the start router, and then load the IOS POST: stored in the ROM of the micro-code, used to check the hardware basic configuration is normal, then to decide which interface is available ROM monitor: stored in the ROM of the micro-code, the role of test and suspect other exclusive Mini-IOS: Cisco call RXBOOT or bootloader, which is stored in the ROM in, IOS simplified version, used to IOS is loaded into the flash memory in the RAM (random-access memory): to save the data packet cache, ARP cache, routing tables, and running-config configuration file. some of the router on, IOS can run from RAM
Platform: | Size: 10240 | Author: rocky | Hits:

[ARM-PowerPC-ColdFire-MIPS] cache

Description: cache设计，直接映射，回写式cache。256行，每行四字。 ram按字存储，大小为64K字。-cache design, direct mapped, write-back cache. 256 lines of four characters. ram memory by the word, the word size is 64K.
Platform: | Size: 29696 | Author: mable | Hits:

[VHDL-FPGA-Verilog] mem-opt_final

Description: memory optimisation cache memory, RAM,SRAM, main memory related doc and ppt attached
Platform: | Size: 985088 | Author: Mahesh | Hits:

[Software Engineering] cache

Description: cache n. 高速缓冲存储器 一种特殊的存储器子系统，其中复制了频繁使用的数据以利于快速访问。存储器的高速缓冲存储器存储了频繁访问的 RAM 位置的内容及这些数据项的存储地址。当处理器引用存储器中的某地址时，高速缓冲存储器便检查是否存有该地址。如果存有该地址，则将数据返回处理器；如果没有保存该地址，则进行常规的存储器访问。因为高速缓冲存储器总是比主RAM 存储器速度快，所以当 RAM 的访问速度低于微处理器的速度时，常使用高速缓冲存储器。-cache n. a special cache memory subsystem, which replicated the frequently used data for fast access. Cache memory stores frequently accessed RAM locations and the contents of the memory address of these data items. When the processor references an address in memory, the cache will check if there is the address. If there is the address, it will return the data processor If you do not save the address, the routine memory access. Because cache memory is always faster than main RAM memory, so when the RAM access speed than the speed of the microprocessor, often using high-speed buffer memory.
Platform: | Size: 12288 | Author: dd | Hits:

[VHDL-FPGA-Verilog] ram32

Description: 并行RAM程序，2位并行读取，可以参考用于要求高速缓存的设计。-Parallel RAM program, two parallel reading, you can refer to the cache for the required design.
Platform: | Size: 6144 | Author: YF | Hits:

[Software Engineering] PA1100-datasheet-V1.0.rar

Description: 磁头解码芯片PA1100特性： 　　1、支持单、双、三轨磁条卡解码； 　　2、内置RAM缓存数据； 　　2、使用简单，无需外部阻容； 　　4、支持正反向刷卡； 　　5、支持自动增益； 　　6、超低功耗，读卡电流小于800uA，休眠电流小于1uA； 　　7、读卡速度5-254cm/秒； 　　8、读卡强度30 -200 ISO7811标准； 　　9、采用shift-out串行接口； 　　10、2.7~3.3V供电； 　　11、多种封装。　,Chip features: 1, supports single-, double-, three-track magnetic stripe card decoding 2, built-in RAM cache data 2, simple to use, eliminating the need for an external resistive and capacitive 4, the support of the pros and cons to the credit card 5, to support automatic gain 6 , ultra-low power consumption, the card reader current less than 800uA, Sleep current is less than 1uA Reader Speed ​ ​ 5-254cm/s 8, Card Reader strength of 30 -200 ISO7811 standard 9, shift-out string line interface 10,2.7 ~ 3.3V power supply 11, a variety of packages.
Platform: | Size: 1083392 | Author: lori | Hits:

[WAP develop] 68013FIFO

Description: 读写68013的程序，进行ram缓存操作，很具有参考价值，希望有用-Read 68,013 procedures, ram cache operation, it is very valuable, useful
Platform: | Size: 2500608 | Author: xianbinrao | Hits:
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