Description: 32×32的寄存器堆，它有32个32位的寄存器、两个读端口和一个写端口。该寄存器堆由3个层次共5个模块构成，最低层次的模块是D触发器，中间层次的模块包括32位寄存器、5位地址译码器、32选1多路选通器，顶层模块是寄存器堆模块。设计采用行为建模和结构建模相结合的方法，先用行为建模方法建立低层模块，然后再用结构建模方法搭建高层模块。-32 × 32 of the register file, it has 32 32-bit registers, two read ports and one write port. The register file by the three levels of a total of five modules, the lowest level module is the D flip-flop, middle-level module including 32-bit register, address decoder 5, 32 election more than one way strobe, and top-level module is Register File module. Design using behavioral modeling and structural modeling method of combining the first act of modeling methods used to establish low-level modules, then the structural modeling method to build high-level module. Platform: |
Size: 4096 |
Author:甜 |
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Description: ALTERA Nios II Embedded Evaluation Kit开发板制造商(terasic)提供的多媒体显示板（Terasic Multimedia Touch Panel
Daughter Board (MTDB)）扩展开发包。
里为有两个开源的例子
1.MTDB_SD_Card_Audio,从SD卡中读取WAV文件然后通过DA播放，这个对不SD Card的初学者非常的有用，可以知道使用FPGA SPI来读写SD CARD。
2.MTDB_Systhesizer,使用FPGA来做电子琴，要用FPGA来做合成器的看这个。
国内部分地区的网络对TERASIC封杀，原因不明，这个包是使用代理下载的，非常不容易。-ALTERA Nios II Embedded Evaluation Kit development board manufacturers (terasic) to provide multi-media display boards (Terasic Multimedia Touch Panel Daughter Board (MTDB)) the expansion of the development package. Where for example there are two open source 1.MTDB_SD_Card_Audio, from the SD card and then read the WAV file to play through the DA, the SD Card for the beginner is not very useful, we can see that the use of FPGA SPI read and write to SD CARD. 2.MTDB_Systhesizer, the use of FPGA as organ, synthesizer use FPGA to do the look at this. Internal parts of the network to block TERASIC for reasons unknown, the package is downloaded using a proxy, is not easy. Platform: |
Size: 27464704 |
Author:myfingerhurt |
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Description: FMF VHDL Models
All the FMF models are VHDL 93 and VITAL 2000 compliant and require the VITAL 2000 library for correct compilation. They are designed for timing backannotation by means of an SDF file. The intrinsic delays default to 1 ns. We have a tool to read internal delays from an external file (in XML) and add them to the simulation through a SDF file. The most recent version is written in perl and may be downloaded from the "FMF Tools" area. Timing files are provided for over 11,500 part numbers.
Also in the tools area is the document type definition (dtd) for the timing files.
FMF MAKES NO WARRANTIES ON THE PERFORMANCE OF ANY MODELS IN ITS DATA REPOSITORY. USERS ARE RESPONSIBLE FOR VERIFYING THE ACCURACY OF THE MODELS, SOFTWARE OR TOOLS PROVIDED (TEST SUITES, PACKAGES, TIMING, ETC.). Platform: |
Size: 20480 |
Author:ledo |
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Description: JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter.
This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on).
JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info. -JTAG Tools is a software package which enables working with JTAG-aware (IEEE 1149.1) hardware devices (parts) and boards through JTAG adapter.
This package has open and modular architecture with ability to write miscellaneous extensions (like board testers, flash memory programmers, and so on).
JTAG Tools package is free software, covered by the GNU General Public License, and you are welcome to change it and/or distribute copies of it under certain conditions. There is absolutely no warranty for JTAG Tools. Please read COPYING file for more info.
Platform: |
Size: 957440 |
Author:asdf |
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Description: 程序说明:
本次实验控制开发板上面的SDRAM完成读写功能。
先向SDRAM里面写数据，然后再将数据读出来做比较，如果不匹配就通过LED变亮显示出来，如果一致，LED就不亮。
part1是使用Modelsim仿真的工程
part2是在开发斑上面验证的工程
目录说明:
part1:
part1_32是4m32SDRAM的仿真工程
part1_16是4m16SDRAM的仿真工程
\model文件夹里面是仿真模型
\rtl文件夹里面是源文件
\sim文件夹里面是仿真工程
\test_bench文件夹里面是测试文件
\wave文件夹里面是仿真波形
-Procedure Note: In this experiment, control development board to complete the above SDRAM read and write capabilities. SDRAM write data inside first and then read out the data to compare, if you do not match on the adoption of LED variable light display, if agreed, LED does not light. part1 is to use Modelsim simulation project part2 the top spot verification in the development of the project directory Description: part1: part1_32 is 4m32SDRAM simulation project part1_16 is 4m16SDRAM simulation works \ model folder, which is a simulation model \ rtl folder, which is the source file \ sim is a simulation project inside the folder \ test_bench folder which is a test file \ wave inside the folder is a simulation waveform Platform: |
Size: 779264 |
Author:军军 |
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Description: 从文件中读取波形文件的testbench例子，大家可以参考-Read from the file testbench waveform file example, we can refer to Platform: |
Size: 1024 |
Author:陈乾 |
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Description: This an DE2 card software, which is able to read some Audio file from a memory (Flash for example).
Extendable to read from a SD card, and to write on it.-This is an DE2 card software, which is able to read some Audio file from a memory (Flash for example).
Extendable to read from a SD card, and to write on it. Platform: |
Size: 76800 |
Author:Minimus |
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Description: CPU86 - Free VHDL CPU8088 IP core
Copyright (C) 2005-2010 HT-LAB
Quick run:
1) Open a DOSBox/Cygwin shell
2) Navigate to the web_cpu88/Modelsim directory.
3) Execute run.bat
See website for more details.
The CPU86 core is released under the GNU GPL license. For more information read the copying.txt
file located in this directory.-CPU86 - Free VHDL CPU8088 IP core
Copyright (C) 2005-2010 HT-LAB
Quick run:
1) Open a DOSBox/Cygwin shell
2) Navigate to the web_cpu88/Modelsim directory.
3) Execute run.bat
See website for more details.
The CPU86 core is released under the GNU GPL license. For more information read the copying.txt
file located in this directory. Platform: |
Size: 562176 |
Author:Dhaval |
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Description: It is a VHDL code for Text file reading which reads a code for In.txt file and which produces output in out.txt file by IEEE file read and writing lecture. Platform: |
Size: 2048 |
Author:bhado |
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Search - read a file VHDL