Search - reed solomon vhdl

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[VHDL-FPGA-Verilog] RS(32to28)encoderanddecoder DL : 1: RS(32,28) encoder and decoder VHDL-RS (32,28) encoder and decoder VHDL
Date : 2025-07-04 Size : 75kb User : 王文
[Windows Develop] MC-ACT-RSENC_DS DL : 0: MemecCoreReed-Solomon coding is a method of forward error correction in the form of block coding. Block coding consists of calculating a number of parity symbols over a number of message symbols. The parity symbols are appended to the end of the message symbols forming a codeword. Reed-Solomon coding is described in the form RS(n,k), where k is the number of message symbols in each block and n is the total number of symbols in the codeword. The value t defines the number of symbols that can be corrected by the Reed-Solomon code, where t=(n-k)/2 and the number of parity symbols is equal to 2t.
Date : 2025-07-04 Size : 93kb User : 张波
[VHDL-FPGA-Verilog] RS(31-19-6) DL : 0: reed-solomon译码器。共有7个文件，分别为译码器的7个模块。-reed-solomon decoder. A total of seven papers, respectively, the decoder module 7.
Date : 2025-07-04 Size : 9kb User : liwei
[Other] RSOriginal DL : 0: Reed-Solomon 信道编码广泛应用于DVB中-Reed-Solomon channel coding are widely used in DVB
Date : 2025-07-04 Size : 11.22mb User : 陈孙阳
[Software Engineering] rsenc DL : 0: this the code for reed solomon encoder of type 7,3. this is the main module program.-this is the code for reed solomon encoder of type 7,3. this is the main module program.
Date : 2025-07-04 Size : 1kb User : alok
[Software Engineering] mult2 DL : 0: this the multiplier 2 module for the reed solomon encoder-this is the multiplier 2 module for the reed solomon encoder
Date : 2025-07-04 Size : 1kb User : alok
[Software Engineering] mult4 DL : 0: this the multiplier 4 module for the reed solomon encoder-this is the multiplier 4 module for the reed solomon encoder
Date : 2025-07-04 Size : 1kb User : alok
[Industry research] VLSI_Architectures_for_ECC DL : 1: This thesis devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.-This thesis is devoted to several efficient VLSI architecture design issues in errorcorrecting coding, including finite field arithmetic, (Generalized) Low-Density Parity- Check (LDPC) codes, and Reed-Solomon codes.
Date : 2025-07-04 Size : 1.02mb User : MicroSam
[Other systems] reed DL : 0: this the completedocumentation and code about reed solomon logic implemented on fpga in verilog.-this is the completedocumentation and code about reed solomon logic implemented on fpga in verilog.
Date : 2025-07-04 Size : 1.79mb User : kamranmu
[VHDL-FPGA-Verilog] RS DL : 0: reed selemon encoder vhdl code
Date : 2025-07-04 Size : 76kb User : mohamed saad
[Communication] RS_Encoder DL : 0: its a reed solomon encoder-its a reed solomon encoder.....
Date : 2025-07-04 Size : 121kb User : haroon
[VHDL-FPGA-Verilog] rstk-0.7.tar DL : 0: archivo reed solom para utilizar en decodificacion de television digital esta en vhdl
Date : 2025-07-04 Size : 174kb User : Gus
[VHDL-FPGA-Verilog] RS_decoder DL : 0: Reed solomon decoder based on table-lookup method VHDL code
Date : 2025-07-04 Size : 4kb User : shahifaqeer
[Books] Errorcontrolcoding DL : 0: 信道编码非常有用的一本书，可以供通信方面的参考一下-　A reorganized and comprehensive major revision of a classic book, this edition provides a bridge between introductory digital communications and more advanced treatment of information theory. Completely updated to cover the latest developments, it presents state-of-the-art error control techniques. Coverage of the fundamentals of coding and the applications of codes to the design of real error control systems. Contains the most recent developments of coded modulation, trellises for codes, soft-decision decoding algorithms, turbo coding for reliable data transmission and other areas. There are two new chapters on Reed-Solomon codes & concatenated coding schemes. Also contains hundreds of new and revised examples and more than 200 illustrations of code structures, encoding and decoding circuits and error performance of many important codes and error control coding systems. Appropriate for those with minimum mathematical background as a comprehensive reference for coding theory.
Date : 2025-07-04 Size : 20.75mb User : vidivici
[Other] rsencoder_latest.tar DL : 0: reed solomon encoder (255,239) verilog source code
Date : 2025-07-04 Size : 4kb User : 梅国强
[VHDL-FPGA-Verilog] read_solomon DL : 0: This project implements a parameterized Reed Solomon decoder for use in OFDM wireless systems.
Date : 2025-07-04 Size : 7kb User : FPGACore
[VHDL-FPGA-Verilog] rsvhdl_255_239 DL : 0: a VHDL implementation of 255_239 reed solomon encoder.
Date : 2025-07-04 Size : 3kb User : saad
[VHDL-FPGA-Verilog] reed_solomon_decoder_latest.tar DL : 0: reed solomon (204,188). in verilog.
Date : 2025-07-04 Size : 175kb User : Evgeny
[VHDL-FPGA-Verilog] rs_dec_enc_latest.tar DL : 0: Reed-Solomon (255,251). in VHDL.
Date : 2025-07-04 Size : 90kb User : Evgeny
[VHDL-FPGA-Verilog] RS_DesignNote DL : 0: Reed-solomon decoder, encoder design note
Date : 2025-07-04 Size : 883kb User : Seok Hoon Shin

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