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[Crack Hack] rijndaelimplemetation

Description: rijndael算法的一个vhdl语言编写的程序,可供学习者参考交流-a VHDL language procedures, exchange of information for learners
Platform: | Size: 7267 | Author: xkl | Hits:

[Crack Hack] rijndaelimplemetation

Description: rijndael算法的一个vhdl语言编写的程序,可供学习者参考交流-a VHDL language procedures, exchange of information for learners
Platform: | Size: 7168 | Author: xkl | Hits:

[VHDL-FPGA-Verilog] AEScoremodules

Description: AES decoder aes_dec.vhdl AES encoder aes_enc.vhdl Package used by rest of design aes_pkg.vhdl Key Expansion component for AES encoder and decoder key_expansion.vhdl -AES AES encoder decoder aes_dec.vhdl aes_ enc.vhdl Package used by rest of design aes_pkg . vhdl Key Expansion component for a AES encoder nd decoder key_expansion.vhdl
Platform: | Size: 10240 | Author: 许茹芸 | Hits:

[Program doc] Rijndael

Description: AES USING PICOBLAZE CODE
Platform: | Size: 17408 | Author: sruthi | Hits:

[VHDL-FPGA-Verilog] aes_core_latest-1.tar

Description: Simple AES (Rijndael) balance implementation and trade off size and performance-Simple AES (Rijndael) balance implementation and trade off size and performance
Platform: | Size: 137216 | Author: FPGACore | Hits:

[VHDL-FPGA-Verilog] aes-vhdl

Description: 使用vhdl语言实现aes（rijndael 算法），程序整体封装成为一个package，方便调用-Using vhdl language aes (rijndael algorithm), the program as a whole package as a package, easy call
Platform: | Size: 7168 | Author: Bruce Lee | Hits:

[Other] A-VHDL-Implemetation-of-the-Advanced-Encryption-S

Description: A VHDL Implemetation of the Advanced Encryption Standard-Rijndael Algorithm
Platform: | Size: 24576 | Author: ram | Hits:

[VHDL-FPGA-Verilog] Coding Files

Description: We present an efficient hardware architecture design & implementation of Advanced Encryption Standard AES Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology NIST of United States has been widely accepted. All the cryptographic algorithms developed can be implemented with software or built with pure hardware. However with the help of Field Programmable Gate Arrays FPGA we tend to find expeditious solution and which can be easily upgraded to integrateany concordat changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language VHDL. Optimized and Synthesizable VHDL code is developed for the implementation of both 128-bit data encryption and decryption process.
Platform: | Size: 27648 | Author: kutti | Hits:

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