Search - rom in vhdl

[VHDL-FPGA-Verilog] 8bitsine

Description: 8bit采样sine波形发生器,一共两个文件，各自用VHDL和VERILOG编写，通信开发平台专用-8bit sampling sine wave generator, a total of two papers, each with VHDL and VERILOG preparation, communications development platform dedicated
Platform: | Size: 5120 | Author: 王刚 | Hits:

[SCM] PinYin_InputMethod_C51

Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Platform: | Size: 14336 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2048 | Author: nick | Hits:

[MiddleWare] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件-FPGA in VHDL ram the classic procedure, applicable to the company ALTERA devices
Platform: | Size: 1024 | Author: gcy | Hits:

[VHDL-FPGA-Verilog] rom

Description: 基于vhdl的rom的描述,经过确定测试通过.-Based on the VHDL description of the rom, after determining the test.
Platform: | Size: 1024 | Author: stone | Hits:

[VHDL-FPGA-Verilog] 64×8bitROM

Description: 64×8bit 的ROM设计，VHDL语言，在ISE可以运行。-64 × 8bit the ROM design, VHDL language, can run in the ISE.
Platform: | Size: 4096 | Author: 张军 | Hits:

[VHDL-FPGA-Verilog] 32×8bitROM

Description: 32×8bit的ROM设计，VHDL语言，在ISE可以运行。-32 × 8bit the ROM design, VHDL language, can run in the ISE.
Platform: | Size: 4096 | Author: 张军 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[Other] 11

Description: NCO 在信号处理方面有着广泛的应用。而函数发生器是NCO 中的关键部分，本文基于FPGA 用状态机和流水线方法实现了CORDIC 算法，并取代了传统的ROM 查找表法。最后通过Quartus II 软件给出仿真结果，验证了理论的正确性。-NCO in the Signal Processing has a wide range of applications. The function generator is a critical part of NCO, the paper-based FPGA using state machine implementation of the Ways and pipelining CORDIC algorithm, and replaces the traditional ROM look-up table method. Finally through the Quartus II software give simulation results to verify the correctness of the theory.
Platform: | Size: 164864 | Author: LEO | Hits:

[VHDL-FPGA-Verilog] FPGA_Examples

Description: 《FPGA嵌入式应用系统开发典型实例》-书的光盘资料，该资料是用VHDL语言编写，作者：叶淦华-" FPGA embedded applications typical example of system development" - the book' s CD-ROM, the information is written in VHDL, the author:叶淦China
Platform: | Size: 8140800 | Author: LDP | Hits:

[SCM] rom

Description: Rom的读取的Verilog代码，自己编写的，大家参考参考啊-Rom read the Verilog code, I have written, your information ah
Platform: | Size: 1024 | Author: keke | Hits:

[VHDL-FPGA-Verilog] ADC0809VHDL

Description: 8.4 ADC0809 VHDL控制程序见随书所附光盘中文件：ADC0809VHDL程序与仿真。 --文件名：ADC0809.vhd --功能：基于VHDL语言，实现对ADC0809简单控制 --说明：ADC0809没有内部时钟，需外接10KHz~1290Hz的时钟信号，这里由FPGA的系 --统时钟（50MHz）经256分频得到clk1（195KHz）作为ADC0809转换工作时钟。 --最后修改日期：2004.3.20 -8.4 ADC0809 VHDL control procedures, see the book with accompanying CD-ROM in the file: ADC0809VHDL procedures and simulation.- File Name: ADC0809.vhd- features: Based on the VHDL language, to achieve a simple control ADC0809- Description: ADC0809 internal clock does not need external 10KHz ~ 1290Hz clock signal, here by the Department of FPGA- EC clock (50MHz ) by the 256 sub-frequency has been clk1 (195KHz) as ADC0809 clock conversion work.- Last modified date: 2004.3.20
Platform: | Size: 4096 | Author: wangnan | Hits:

[VHDL-FPGA-Verilog] wavegenerator

Description: 开发环境为QuartusII，能产生正弦波、三角波、方波和锯齿波，幅度为5V，采样为8位，在开发板已经验证通过，有详细的波形图和管脚分配图。-Development environment for QuartusII, can generate sine wave, triangle wave, square wave and sawtooth wave, ranging from 5V, sampling for 8, in the development board has to verify is passed, the waveform in detail the distribution of maps and map pins.
Platform: | Size: 498688 | Author: 李海明 | Hits:

[VHDL-FPGA-Verilog] VHDLcodes

Description: Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.- Behavioral description of ALU, RAM MODULE, ROM MODULE, DIVIDE BY N COUNTER, GENERIC DIVIDER 2n+1, GCD CALCULATOR, GCD FSM CODE, JK FLIP FLOP in VHDL . These are fully synthesized codes with optimization.
Platform: | Size: 6144 | Author: Vijay | Hits:

[Other] rom

Description: 64采样点的正弦表存储区。外接地址可以输出正弦信号采样点经过二进制补码转换后的幅度值。-sine table by 64 samples in VHDL.
Platform: | Size: 222208 | Author: nancy | Hits:

[VHDL-FPGA-Verilog] SPI_controller

Description: SPI serial flash ROM的verilog源代码, 针对winbond W25x16,已经经过逻辑验证,并实际用在芯片设计中,作为一个模块,正常工作.-SPI serial flash ROM in verilog source code for winbond W25x16, logic has been verified, and actually used in chip design, as a module to work.
Platform: | Size: 8192 | Author: Jerd Hu | Hits:

[VHDL-FPGA-Verilog] sine-generator

Description: ROM型正弦信号发生器，从rom中读取正弦波的点，循环输出，经AD生成波形，环境为quartus-sine generator in quartus
Platform: | Size: 677888 | Author: 张文 | Hits:

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom
Platform: | Size: 1256448 | Author: 许聪 | Hits:

[VHDL-FPGA-Verilog] fft

Description: 基于VHDL语言编写的FFT程序，256点，旋转因子存在自己编写的ROM里面，乘法器和数据存储采用的是IP核-FFT-based program written in VHDL, 256 points, there is rotation factor which I have written the ROM, multiplier, and data storage is used in IP core
Platform: | Size: 6144 | Author: 胡佳 | Hits:

[VHDL-FPGA-Verilog] 328 ROM module

Description: 32 byte ro0n moudule implementation in vhdl code
Platform: | Size: 2048 | Author: allia | Hits:

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[VHDL-FPGA-Verilog] 8bitsine

[SCM] PinYin_InputMethod_C51

[VHDL-FPGA-Verilog] ram

[MiddleWare] ram

[VHDL-FPGA-Verilog] rom

[VHDL-FPGA-Verilog] 64×8bitROM

[VHDL-FPGA-Verilog] 32×8bitROM

[VHDL-FPGA-Verilog] rom

[Other] 11

[VHDL-FPGA-Verilog] FPGA_Examples

[SCM] rom

[VHDL-FPGA-Verilog] ADC0809VHDL

[VHDL-FPGA-Verilog] wavegenerator

[VHDL-FPGA-Verilog] VHDLcodes

[Other] rom

[VHDL-FPGA-Verilog] SPI_controller

[VHDL-FPGA-Verilog] sine-generator

[VHDL-FPGA-Verilog] FPGA-VHDL-DDS

[VHDL-FPGA-Verilog] fft

[VHDL-FPGA-Verilog] 328 ROM module

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