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[Other resource] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证
Platform: | Size: 651381 | Author: jimmy | Hits:

[Crack Hack] rom_des

Description: DES 加密算法的VHDL和VERILOG 源程序及其TESTBENCH。-VHDL and VERILOG sourcecode and TESTBENCH of DES encrypting algorithm
Platform: | Size: 30720 | Author: | Hits:

[VHDL-FPGA-Verilog] sram

Description: sram 读写小程序，用verilog编写的，请各位高手指教-SRAM read and write small programs using Verilog prepared, please enlighten you master
Platform: | Size: 1024 | Author: kevin | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码 两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] rom_table

Description: rom vector table vhdl and Testbench
Platform: | Size: 172032 | Author: KoBin | Hits:

[VHDL-FPGA-Verilog] jpeg_hardware.tar

Description: 用FPGA实现的JPEG压缩器，可以直接使用，内含完整文档说明-This project features a complete JPEG Hardware Compressor (standard Baseline DCT, JFIF header) with 2:1:1 subsampling, able to compress at a rate of up to 24 images per second at the maximum resolution 352x288 (on XC2V1000-4 @ 40 MHz). IMAGE RESOLUTION IS LIMITED TO 352x288. It takes an RGB input (row-wise) and outputs to a memory the compressed JPEG image with headers. A testbench has been made that takes a bitmap image from your computer and writes a compressed JPEG file by simulating the code. In order to be able to run the project you must first generate the RAM/ROM cores and the DCT2D core with Xilinx CoreGen. The configuration values are listed at the bottom of the file compressor.vhd. If you run into any problems downloading the files from the cvs please check that you are downloading them in binary form. For any questions my email is: victor.lopez [(at)] ono [(dot)] com PLEASE NOTICE THAT THIS CORE IS LICENSED UNDER http://creativecommons.org/licenses/by-nc-sa/3.0/ (Creative Co
Platform: | Size: 868352 | Author: | Hits:

[VHDL-FPGA-Verilog] CoreFIR_RTL-3.0

Description: actelIP核 的fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision-actelIPcore fircore Core Generator – Executable File Outputs Run-Time Library (RTL) Code and Testbench Based on Input Parameters – Self-Checking – Executable Tests Generated Output against Algorithm • Distributed Arithmetic (DA) Algorithm – Multiplier-Free Computation – Low Cost – Optimized for Actel FPGAs • Folding Architecture to Minimize Design Size – Serialized Computation when System Clock Rate is Faster than the Data Sample Rate • Efficient Structure Using Embedded RAMs – Lookup Tables Utilize Embedded RAMs • On-Chip DA Lookup Table Generator for FPGA with Embedded RAMs • Embedded RAMs Initialized as DA Lookup Table • DA Lookup Table ROM Synthesis for FPGA without Embedded RAMs • Multiple DA lookup Tables to Split Large Number of Taps • Actel FPGA-Optimized RTL Code • Supports 2 to 128 Taps • 1- to 32-Bit Input Data and Coefficient Precision
Platform: | Size: 1051648 | Author: 睿宸 | Hits:

[Embeded-SCM Develop] ise_c8051

Description: r8051（c8051）IP源码，使用VHDL编写。整个工程通过ISE13.2实现，附带完整testbench，并实例化了rom和ram，可以运行c代码。工程内包含modelsim的仿真脚本，可以观测程序运行时的内部硬件工作情况。-r8051 (c8051) IP source code, the use of VHDL. The whole project is realized by ISE13.2, with complete testbench, and examples of the rom and ram, you can run the c code. Modelsim simulation scripts contained within the project, the work of the internal hardware can be observed when the program is running.
Platform: | Size: 6135808 | Author: woody.wu | Hits:

[Other] pud_ben

Description: Verilog HDL source code of generating a ROM file (in Quartuss) and testbench in Modelsim (verification)
Platform: | Size: 5120 | Author: Ben | Hits:

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