Search - rom vh

[VHDL-FPGA-Verilog] dcm

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 10240 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 一个 16×8bit 的ROM程序包括程序的初始化。-A 16 × 8bit the ROM initialization procedures, including procedures.
Platform: | Size: 3072 | Author: h13978699183 | Hits:

[VHDL-FPGA-Verilog] rom

Description: 我用VHDL写的正弦，用FPGA内部ROM，有仿真testbench,在quartus里可以运行。在板子里已经验证-I used to write VHDL sinusoidal, using FPGA internal ROM, has simulation testbench, you can run in Quartus. Yard has already been verified in the plates
Platform: | Size: 651264 | Author: jimmy | Hits:

[VHDL-FPGA-Verilog] cc2420interfacecs

Description: 对cc2420无线模块的接口。接受到的数据都使用双口ROM的方式与后台核心控制部分传送。-On the CC2420 radio module interface. Receive data using dual-port ROM with the core control part of the background transmission.
Platform: | Size: 5287936 | Author: 陈送 | Hits:

[VHDL-FPGA-Verilog] DW8051_ALL

Description: 包中包括, DW8051完整的Verilog HDL代码两本手册: DesignWare Library DW8051 MacroCell, Datasheet DesignWare DW8051 MacroCell Databook 三篇51论文: 基于IP 核的PSTN 短消息终端SoC 软硬件协同设计 Embedded TCP/ IP Chip Based on DW8051 Core 以8051为核的SOC中的万年历的设计 -DW8051 is designed by synopsys, and its instruction cycle is 4 clock, which lead to about 3 times faster than Intel 8051 with the same oscillator frequency. I writed ram, rom, some other perpherals such as DES, RNG, and its testbench, and it worked all right!
Platform: | Size: 1588224 | Author: myfingerhurt | Hits:

[VHDL-FPGA-Verilog] oc_i2c_master

Description: I 2 C 是两线双向的串行接口，非常适合芯片级的通讯。由于 SOPC Builder并未提供 I 2 C 内核，本节所描述的 I 2 C 内核是 Richard Herveille 制作的并发布到网上去的免费核。关于 I 2 C 核的使用方法，请见光盘中 oc_i2c_master文件夹下的使用说明.txt。 -I 2 C is a 2-line bidirectional serial interface, very suitable for chip-level communication. Because SOPC Builder does not provide I 2 C core, as described in this section I 2 C core is produced by Richard Herveille and publish to the web free of charge to go nuclear. With regard to I 2 C core to use, see the CD-ROM folder oc_i2c_master use instructions. Txt.
Platform: | Size: 260096 | Author: xuai | Hits:

[VHDL-FPGA-Verilog] URISC

Description: 一个完整的带I/O和RAM，ROM的URISC,可以完成A+B/2的运算。实际上，通过对ROM的手工编程，可以实现8为数据的加减乘除，已经更加复杂的运算。-An ultimate URISC With I/Os, a RAM, a ROM,which can complete A+ B/2 calculations. In fact, through the ROM of the manual programming, it can do more calculations,such as A+B,A-B,A*B,A/B,and so on.
Platform: | Size: 5120 | Author: 王斌 | Hits:

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[VHDL-FPGA-Verilog] dcm

[VHDL-FPGA-Verilog] rom

[VHDL-FPGA-Verilog] rom

[VHDL-FPGA-Verilog] cc2420interfacecs

[VHDL-FPGA-Verilog] DW8051_ALL

[VHDL-FPGA-Verilog] oc_i2c_master

[VHDL-FPGA-Verilog] URISC

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