Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all. Platform: |
Size: 20480 |
Author:daiowen |
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Description: 用FPGA实现RS232通信,此代码是用VHDL语言编写，非常有用的好东东啊-RS232 Communication with FPGA realize that this code is written in VHDL, very useful, good东东啊 Platform: |
Size: 48128 |
Author:孙建军 |
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Description: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。
-杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules. Platform: |
Size: 92160 |
Author:Wuxinmin |
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Description: Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd - to display at 7 sgement display
- D4to7 .vhd - Convert HEX decimal to ASCII code.
-Working RS232 controller running at 9600 Hz.
Consist of Transmitter and Receiver Module.
Tested in FPGA Spartan 3
Included files for testing at FPGA
- Scan4digit .vhd- to display at 7 sgement display
- D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: |
Size: 5120 |
Author:Ikki |
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Description: 用FPGA实现RS232，代码经过测试通过-FPGA implementation using RS232, the code has been tested through Platform: |
Size: 3072 |
Author:treefan.liang |
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Description: 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform. Platform: |
Size: 13312 |
Author:弘历 |
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Description: 包含了8051rs232设计的全部源码，可直接应用于sopc/FPGA设计中。-Contains all the source code 8051rs232 design can be directly applied to sopc/FPGA design. Platform: |
Size: 6845440 |
Author:anchor |
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Description: RS232串口通讯在的FPGA应用的v原代码-The v original code of the RS232 serial port communication in FPGA applications Platform: |
Size: 4096 |
Author:wenyangzeng |
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Description: 在altera的FPGA平台上实现rs232串口的自收发通信，速率为115200波特率，PC机使用串口调试助手即可观察结果。包含全部代码与工程，本人亲自测试通过。-Realization of self transmitting and receiving communication serial port of RS232 In altera on the FPGA platform, at a rate of 115200 baud rate, PC using serial debugging assistant can be observed. Contains all the code and engineering, I personally tested by.
Platform: |
Size: 15369216 |
Author:汪少锋 |
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Description: 该文件是在ise开发环境下的代码，实现rs232协议，并在FPGA上验证成功-This file is the code in ise development environment, to achieve rs232 protocol, and authentication succeeds on FPGA Platform: |
Size: 74752 |
Author:许郁冰 |
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Description: 编制一全双工UART电路，通过试验箱MAX202E转换成RS232电平，与计算机进行通讯实验，设置8个按键，按键值为ASIC码“1”~“8”，通过串口发送给计算机，在计算机上显示键值，同时在数码管最高位显示；计算机可发送“0”~“F”的ASIC码，FPGA接收后在数码管低位显示0~F。通过按键可设置波特率。
要求：波特率为三种 1200、2400、9600，由1个按键选择，3个LED分别指示；
数据格式为1位起始位、8位数据位和一位停止位；
上位计算机发送接收软件可使用“串口调试器“软件；
发送和接收数据时，由两个LED分别指示。
发挥：自动回发功能、接收到特殊字符（自定义）自动更改波特率。(A full duplex UART circuit, converted into RS232 level by MAX202E test box, communication experiment with computer, set of 8 buttons, keys for ASIC code "1" to "8", to the computer through the serial port to send and display keys on the computer, at the same time in the digital tube display high computer can send "; 0" to "F" in the ASIC code, FPGA after receiving the digital tube display low 0~F. You can set the baud rate by the button.
Requirements: baud rate for three, 1200, 2400, 9600, selected by 1 buttons, 3 LED, respectively;
The data format consists of 1 bit start bits, 8 bit data bits, and one stop bit;
The upper computer sends and receives the software, and the serial debugger can be used;
When sending and receiving data, instructions are given by two LED respectively.
Play: Auto postback function, receive special characters (custom), change baud rate automatically.) Platform: |
Size: 2948096 |
Author:淡淡的意识
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