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[Other resource] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 162360 | Author: lq | Hits:

[Other resource] vhdl

Description: RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
Platform: | Size: 4406 | Author: 波波 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: RS232数据发送器,适合于VHDL的初学者参考-RS232 data transmitter, suitable for beginners VHDL reference
Platform: | Size: 4096 | Author: 波波 | Hits:

[VHDL-FPGA-Verilog] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 161792 | Author: lq | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Embeded-SCM Develop] rs232lan

Description: CPLD 9536 程序 我自己用的代码. VHDL语言-CPLD 9,536 procedures for my own use code. VHDL
Platform: | Size: 621568 | Author: 罗明 | Hits:

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] Verilog_example

Description: 本文件包括多路选择器器建模，译码器实验程序，加法器实验程序，比较器实验程序，计数器建模，I2C接口标准建模源码，串行接口RS232标准建模源码标准，LCM建模源码，时钟６分频源码，串并转化源码。 ，对于硬件设计初学者来说有一定的参考价值。-This document includes MUX device modeling, experimental procedure decoder, adder experimental procedures, experimental procedures comparators, counters modeling, I2C interface standard modeling source, standard RS232 serial interface modeling source standards, LCM modeling source, clock frequency source 6, and transforming source string. For hardware design beginners have a certain reference value.
Platform: | Size: 1064960 | Author: 朱秋玲 | Hits:

[VHDL-FPGA-Verilog] UART

Description: 用FPGA实现了RS232异步串行通信，所用语言是VHDL，另外本人还有Verilog的欢迎交流学习，根据RS232 异步串行通信来的帧格式，在FPGA发送模块中采用的每一帧格式为：1位开始位+8位数据位+1位奇校验位+1位停止位，波特率为2400。由设置的波特率可以算出分频系数，具体算法为分频系数X=CLK/(BOUND*2)。-Using FPGA to achieve the RS232 asynchronous serial communication, the language used is VHDL, In addition, I also welcome the exchange of learning Verilog, according to RS232 asynchronous serial communication to the frame format, in the FPGA module used to send each frame format : the beginning of a bit+ 8-bit data bit+ 1 bit odd parity bit+ 1 bit stop bit, baud rate for 2400. By setting the baud rate can be calculated at the frequency coefficient, the specific algorithm for the sub-frequency coefficient X = CLK/(BOUND* 2).
Platform: | Size: 1024 | Author: saibei007 | Hits:

[Com Port] serialrxtx

Description: 个人原创，已经测试通过。功能：完成串行数据与RS232格式数据的收发转换，ST16C450+串并双向转换兼收发时序产生功能，优点：省去了传统的ST16C450需要CPU干预的缺点，简化设计， 纯硬件自动转换，缺点：忽略各种异常报警，适用于误码测试时使用（传输错误由误码测试功能模块完成检测）。-Personal originality, have the test. Function: the completion of serial data and send and receive RS232 data format conversion, ST16C450+ String and two-way conversions and transceivers generate timing features, advantages: eliminating the traditional need for CPU intervention ST16C450 shortcomings, simplify the design, pure hardware automatically converted, disadvantages: ignore the various abnormal alarm, error test applies to the use of (transmission errors by the error detection test function modules completed).
Platform: | Size: 26624 | Author: fg0112 | Hits:

[VHDL-FPGA-Verilog] RS232_pro

Description: RS232 verilog coding 全参数化设计 可以自己设定波特率 时钟频率等 完全FPGA实现调通-RS232 verilog coding the entire parametric design can set the baud rate clock frequency of FPGA to achieve complete transfer pass
Platform: | Size: 2048 | Author: dinsh | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[Embeded-SCM Develop] RS232.VHDL

Description: RS232 Communication function in VHDL for Spartan 3E
Platform: | Size: 1024 | Author: Tony Tan | Hits:

[Driver Develop] Rs232_Recv2

Description: controller RS232 for receiving serial data at different speeds
Platform: | Size: 1024 | Author: Natacho | Hits:

[Program doc] async_transmitter

Description: 该程序为RS232串口通信的VERILOG程序，在FPGA上已通过验证，在测试范围内误码率为0-The program for the RS232 serial port communications VERILOG procedures, the FPGA has been validated in the test range of bit error rate is 0
Platform: | Size: 1024 | Author: su | Hits:

[Embeded-SCM Develop] rs232

Description: rs232 interface for xilinx spartan 3e
Platform: | Size: 8192 | Author: MILIND | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Platform: | Size: 13312 | Author: 弘历 | Hits:

[Com Port] RS232

Description: simple example for uart on fpga
Platform: | Size: 714752 | Author: Jay | Hits:

[VHDL-FPGA-Verilog] Rs232-reciever

Description: RS232 reciver vhdl code for RS232 EIA232-RS232 reciver vhdl code for RS232 EIA232
Platform: | Size: 2048 | Author: sgma | Hits:

[SCM] RS232--TEST--VHDL

Description: 自己编写的程序，自己做的板子，并且调试成功了，可以下载使用的很好的测试程序。-I have written a program, do their own board and debugging successful, the program can be downloaded for use. .
Platform: | Size: 4096 | Author: 林木 | Hits:
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