Search - rs232 vhdl code

[VHDL-FPGA-Verilog] vhdl-2

Description:
Platform: | Size: 59392 | Author: lileiming | Hits:

[VHDL-FPGA-Verilog] RS232-for-vdhl

Description: RS232通讯VHDL源代码,MAXPLUS 2环境执行通过-RS232 communications VHDL source code, Segments 2 environment through implementation
Platform: | Size: 161792 | Author: lq | Hits:

[VHDL-FPGA-Verilog] generic_fifo

Description: 这是从opencores下的fifo代码,包括了异步和同步的,还有写的testbench,希望对大家有用.-This is opencores fifo under the code, including asynchronous and synchronous. There testbench written in the hope that useful for all.
Platform: | Size: 20480 | Author: daiowen | Hits:

[Embeded-SCM Develop] rs232lan

Description: CPLD 9536 程序我自己用的代码. VHDL语言-CPLD 9,536 procedures for my own use code. VHDL
Platform: | Size: 621568 | Author: 罗明 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: RS232 verilog design
Platform: | Size: 114688 | Author: liuKe | Hits:

[Other Embeded program] RS232

Description: 基于XILINX的内嵌POWERPC的处理器的串行通讯的应用源代码.-XILINX PowerPC-based embedded processor serial communication application source code.
Platform: | Size: 344064 | Author: 王晶 | Hits:

[VHDL-FPGA-Verilog] uart

Description: vhdl语言编写的实现uart协议的程序,用于rs232电气接口程序开发.支持比特率从2400-115200.-VHDL languages realize UART protocol procedures, electrical RS232 interface for program development. to support the bit rate from 2400-115200.
Platform: | Size: 5120 | Author: 陈想 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: quatus II 环境下vhdl实现RS232功能-quatus II environment realize RS232 VHDL functional
Platform: | Size: 437248 | Author: 王艳华 | Hits:

[VHDL-FPGA-Verilog] FPGArealizeRS232

Description: 用FPGA实现RS232通信,此代码是用VHDL语言编写，非常有用的好东东啊-RS232 Communication with FPGA realize that this code is written in VHDL, very useful, good东东啊
Platform: | Size: 48128 | Author: 孙建军 | Hits:

[Com Port] uart(Verilog)

Description: RS232的verilog源代码,如果需要的可以-RS232 of Verilog source code, if necessary can be
Platform: | Size: 10240 | Author: 陈强 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 基于VHDL的RS232通讯程序,包含完整的源代码,锁脚文件以及下载文件,可直接下载使用-VHDL based on the RS232 communication procedures, including complete source code, locking pin, as well as download files documents can be directly downloaded using
Platform: | Size: 16384 | Author: 陈泽涛 | Hits:

[VHDL-FPGA-Verilog] rs232

Description: dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, serial presentation. code test.
Platform: | Size: 121856 | Author: pp | Hits:

[Com Port] UART

Description: 内含有完整的UART代码，包括发送和接受，且有testbench，可以直接仿真调试-Contain complete UART code, including send and receive and there testbench, can directly Simulation debugging
Platform: | Size: 9216 | Author: 李佳 | Hits:

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

Description: 杜晓斌和陈兴文-FPGA和单片机串行通信接口的实现一文提出了FPGA与单片机实现数据串行通信的解决方案。在通信过程中完全遵守RS232 协议，给出了发送模块的vhdl源代码。 -杜晓斌and陈兴文-FPGA single-chip serial communication interface and the realization of a text proposed by the FPGA and MCU serial data communications solutions. In the communication process in full compliance with the RS232 protocol is given to send the VHDL source code modules.
Platform: | Size: 92160 | Author: Wuxinmin | Hits:

[Software Engineering] RS232_TxD_source_code

Description: RS232 Transmitter VHDL Code
Platform: | Size: 1024 | Author: mohd | Hits:

[Software Engineering] TopLevelRS232

Description: TopLevel Rs232 VHDL code
Platform: | Size: 1024 | Author: mohd | Hits:

[Software Engineering] Rs232Rxd

Description: Rs232 Receiver VHDL code
Platform: | Size: 1024 | Author: mohd | Hits:

[VHDL-FPGA-Verilog] Rs232sourcecode

Description: Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd - to display at 7 sgement display - D4to7 .vhd - Convert HEX decimal to ASCII code. -Working RS232 controller running at 9600 Hz. Consist of Transmitter and Receiver Module. Tested in FPGA Spartan 3 Included files for testing at FPGA - Scan4digit .vhd- to display at 7 sgement display - D4to7 .vhd- Convert HEX decimal to ASCII code.
Platform: | Size: 5120 | Author: Ikki | Hits:

[VHDL-FPGA-Verilog] rs232

Description: 完整的RS232 Verilog源代码，支持波特率可调，支持调试命令，配合串口调试工具，可作为FPGA开发中的调试平台。-Full RS232 Verilog source code, support for baud rate is adjustable to support debugging command, with the serial debugging tools can be used as the debugging FPGA development platform.
Platform: | Size: 13312 | Author: 弘历 | Hits:

[VHDL-FPGA-Verilog] RS232

Description: EP2C8Q208_Quartus_V8.0 基于FPGA实现RS232 VHDL代码-EP2C8Q208_Quartus_V8.0 FPGA-based implementation RS232 VHDL code
Platform: | Size: 402432 | Author: zkzkzk | Hits:

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[VHDL-FPGA-Verilog] vhdl-2

[VHDL-FPGA-Verilog] RS232-for-vdhl

[VHDL-FPGA-Verilog] generic_fifo

[Embeded-SCM Develop] rs232lan

[VHDL-FPGA-Verilog] rs232

[Other Embeded program] RS232

[VHDL-FPGA-Verilog] uart

[VHDL-FPGA-Verilog] RS232

[VHDL-FPGA-Verilog] FPGArealizeRS232

[Com Port] uart(Verilog)

[VHDL-FPGA-Verilog] RS232

[VHDL-FPGA-Verilog] rs232

[Com Port] UART

[Books] ComunicationRealizationBetweenFPGAandSerialInterfa

[Software Engineering] RS232_TxD_source_code

[Software Engineering] TopLevelRS232

[Software Engineering] Rs232Rxd

[VHDL-FPGA-Verilog] Rs232sourcecode

[VHDL-FPGA-Verilog] rs232

[VHDL-FPGA-Verilog] RS232

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