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Description: uart VHDL code : include tx,rx,parity bit control
Platform: |
Size: 13312 |
Author: byungchan |
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Description: 该工程用verilog编写，已通过串口调试助手调试通过，接收模块采用8倍波特率采样数据，有较好的滤波功能，在PC上完成自发自收功能。-Verilog prepared by the project, has passed through the serial debug debugging assistant, receiving 8 times the baud rate module sampling data, a better filtering in the PC to complete the voluntary self-close feature.
Platform: |
Size: 1312768 |
Author: eric |
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