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Description: 本文档是关于采样保持芯片398的官方datasheet。对A/D转换方面有所帮助。-This document is on-chip Sample and Hold 398 official datasheet. On the A/D conversion help.
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Size: 81920 |
Author: 陈 |
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Description: 高速采样保持放大器AD781，最适合刚刚的初学者-High-speed sample-and-hold amplifier AD781, the most suitable for the beginner just
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Size: 71680 |
Author: zhangfeng |
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Description: Simulador, sistema conversor Analogico digital y viceversa. Conceptos de Sample and hold, muestreo instantaneo y natural. (Analisis de polos ceros, respuesta en frecuencia y senales en el tiempo)
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Size: 205824 |
Author: CidLuck |
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Description: Código que implementa modulaç ã o PAM com sample-and-hold
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Size: 1024 |
Author: Nery |
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Description: muestreo por la tecnica sample and hold de una señ al diente de sierra
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Size: 5120 |
Author: diego_ddgm |
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Description: Bit Error Rate analysis of an Extended Receiver for Rectangular PAM.
The performance of a digital communication system in the presence of additive white Gaussian noise (AWGN) can be assessed by the measurement of the bit error rate (BER). The Simulink model provided is a rectangular polar pulse amplitude modulation (PAM) baseband system with an AWGN channel and an extended sample and hold receiver with a low pass filter.
An extended receiver has an odd number of sample and hold circuits. What remains to be answered is if such a receiver would provide a more desirable BER than that of a simple S/H receiver.-Bit Error Rate analysis of an Extended Receiver for Rectangular PAM.
The performance of a digital communication system in the presence of additive white Gaussian noise (AWGN) can be assessed by the measurement of the bit error rate (BER). The Simulink model provided is a rectangular polar pulse amplitude modulation (PAM) baseband system with an AWGN channel and an extended sample and hold receiver with a low pass filter.
An extended receiver has an odd number of sample and hold circuits. What remains to be answered is if such a receiver would provide a more desirable BER than that of a simple S/H receiver.
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Size: 11264 |
Author: Griffin Wright |
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Description: this mdl shows the sample and hold simulation.
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Size: 6144 |
Author: monasubramaniam |
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Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形的单次触发、连续触发和存储回放功能，并按要求进行了垂直灵敏度和扫描速度的挡位设置。信号采集时，将外部输入信号经信号调理模块调节到A/D电路输入范围，经A/D转换后送入FPGA内部的双口RAM进行高速缓存，并将结果通过D/A转换送给通用示波器进行显示，完成了对中、低频信号的实时采样和高频信号的等效采样和数据存储回放。经测试，系统整体指标良好，垂直灵敏度和扫描速度等各项指标均达到设计要求。-The problem to design a digital storage oscilloscope, to Xilinx, 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, internal trigger, A/D converter, D/A conversion and I/O modules) the use of VHDL language programming, arbitrary waveform one-shot, continuous playback is triggered, and storage, in accordance with the requirements of the vertical sensitivity and sweep speed of the gear set. Signal acquisition, it will be the external input signal conditioning by the signal conditioning modules to the A/D circuit input range, after A/D converted into the FPGA s internal dual-port RAM for high-speed cache, and the results through the D/A converter to give general oscilloscope shows completed, the low-frequency signals in real-time sampling and high-frequency signals equivalent sampling and data storage playback. Been tested, the system as a whole indices are good, the vertical sensitivity and scan speed indicators meet
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Size: 546816 |
Author: 黄奇家 |
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Description: by the sensor isolation ... E. Sample and Hold Circuit. Three-phase unbalanced measurement must be ... CCS has integrated visualization code ...
doi.ieeecomputersociety.org/10.1109/ISCID.2009.232
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Size: 1496064 |
Author: farshid |
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Description: LF398采样保持器，由双极性绝缘栅场效应管组成，它具有采样速度快、保持下降速度慢、精度高等特点，采样时间小于6μs时精度可达O.01％；采用双极性输入状态可获得低偏置电压和宽频带；抗干扰能力强，不易受温度影响；芯片上的逻辑输入端均为具有低输入电流的差动输入，允许直接与TTL、PMOS和CMOS相连，差动门限为1.4 V，电源电压可在士5 V和±18 V之间变化．-LF398 sample and hold device, the insulated gate bipolar field effect transistor formed, it has a sampling speed, to keep down slow, high precision, when the sampling time is less than 6μs accuracy up to O.01 with bipolar input state can achieve low offset voltage and wide bandwidth anti-interference ability, easily affected by temperature chip logic inputs are differential with low input current input, allowing direct and TTL, PMOS and CMOS linked differential threshold is 1.4 V, power supply voltage of ± 5 V and ± 18 V between the changes.
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Size: 57344 |
Author: 梁珠 |
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Description: 采样保持电路中全差分运算放大器的设计与仿真-Sample and hold circuit of Fully Differential Operational Amplifier Design and Simulation
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Size: 658432 |
Author: Ranking |
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Description: 本题设计一个数字存储示波器，以Xilinx公司20万门FPGA芯片为核心，辅以必要的外围电路（包括信号调理、采样保持、内部触发、A/D转换、D/A转换和I/O模块），利用VHDL语言编程，实现了任意波形-The problem to design a digital storage oscilloscope, to Xilinx, Inc. 200,000 FPGA chip as the core, supplemented by the necessary peripherals (including signal conditioning, sample and hold, the internal trigger, A/D converter, D/A conversion and I/O modules) using VHDL language programming, the arbitrary waveform
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Size: 14336 |
Author: Jasen |
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Description: 本文是采样保持芯片AD781和AD783的芯片资料，该芯片在信号的采集以及AD转换具有重要的用途-This is a sample and hold chip AD781 chip data, the chip in the signal acquisition and has an important use AD Conversion
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Size: 750592 |
Author: 杨前 |
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Description: The modular method for the reconstruction of sample and hold interpolated signals
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Size: 289792 |
Author: sina |
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Description: A timing error detector for Communication systems with simulink.
# Required versions Matlab 5.2.1, Simulink 2.2.1
# File description
1. ti_det1.m (simulink version 5.2.1)
An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller,
Timing recovery in digital synchronous data receivers,
IEEE Trans. Comun., vol COM-24, no. 5, May 1976.
2. m_delay3.m (related m-file)
An s-function operating as sample and hold with clock port.
3. test1.mdl
A timing recovery system to test the timing detector.
-A timing error detector for Communication systems with simulink.
# Required versions Matlab 5.2.1, Simulink 2.2.1
# File description
1. ti_det1.m (simulink version 5.2.1)
An s-function to be used for timing detector. For detailed information, Refer to the following paper,K.H. Mueller and M. Mueller,
Timing recovery in digital synchronous data receivers,
IEEE Trans. Comun., vol COM-24, no. 5, May 1976.
2. m_delay3.m (related m-file)
An s-function operating as sample and hold with clock port.
3. test1.mdl
A timing recovery system to test the timing detector.
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Size: 156672 |
Author: juyayayo |
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Description: 低电源电压范围为1.8 V至3.6 V
超低功耗：
- 主动模式：280μA，在1 MHz，2.2伏
- 待机模式：1.1μA
- 关闭模式（RAM保持）：0.1μA
五省电模式
欠待机模式唤醒
超过6微秒
16位RISC架构，
125 ns指令周期时间
12位A/ D转换器具有内部
参考，采样和保持，并
AutoScan功能
16位Timer_B随着三† 或七‡
捕捉/比较随着阴影寄存器
具有三个16位定时器A
捕捉/比较寄存器
片上比较器
串行通信接口（USART），
选择异步UART或
同步SPI软件：
- 两个USART（USART0 USART1）的†
- 一个USART（USART0）‡
掉电检测
电源电压监控器/监视器
可编程电平检测
串行板载编程，
无需外部编程电压
安全可编程代码保护
融合-Low Supply-Voltage Range, 1.8 V to 3.6 V
Ultralow-Power Consumption:
− Active Mode: 280 µ A at 1 MHz, 2.2 V
− Standby Mode: 1.1 µ A
− Off Mode (RAM Retention): 0.1 µ A
Five Power Saving Modes
Wake-Up From Standby Mode in Less
Than 6 µ s
16-Bit RISC Architecture,
125-ns Instruction Cycle Time
12-Bit A/D Converter With Internal
Reference, Sample-and-Hold and
Autoscan Feature
16-Bit Timer_B With Three† or Seven‡
Capture/Compare-With-Shadow Registers
16-Bit Timer_A With Three
Capture/Compare Registers
On-Chip Comparator
Serial Communication Interface (USART),
Select Asynchronous UART or
Synchronous SPI by Software:
− Two USARTs (USART0, USART1)†
− One USART (USART0)‡
Brownout Detector
Supply Voltage Supervisor/Monitor With
Programmable Level Detection
Serial Onboard Programming,
No External Programming Voltage Needed
Programmable Code Protection by Security
Fuse
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Size: 1932288 |
Author: 苏春明 |
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Description: LTC1099 高速AD芯片Fast Conversion Time: 2.5μs-The LTC
1099 is a high speed microprocessor compatible
8-bit analog-to-digital converter (A/D). An internal sample-
and-hold (S/H) allows the A/D to convert inputs up to the
full Nyquist limit. With a conversion rate of 2.5μs, this
allows 156kHz 5VP-P input signals or slew rates as high as
2.5V/μs, to be digitized without the need for an external
S/H.
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Size: 176128 |
Author: 刘强 |
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Description: 采样保持放大器电路，时钟频率20KHz，孔径抖动200ps-Sample-and-hold amplifier circuit, the clock frequency of 20KHz, aperture jitter 200ps
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Size: 1024 |
Author: overmars |
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Description: AD10制作的采样保持电路原理图及PCB板，超精致！-AD10 production sample and hold circuit schematics and PCB board, super fine!
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Size: 276480 |
Author: 刘银龙 |
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Description: AD9690英文数据手册
AD9690是一款14位、1 GSPS模数转换器(ADC)。 该器件内置片内缓冲器和采样保持电路，专门针对低功耗、小尺寸和易用性而设计。 该器件设计用于高达2 GHz的宽带模拟信号采样。 AD9690针对宽输入带宽、高采样速率、出色的线性度和小封装低功耗而优化。 -English AD9690 Datasheet AD9690 is a 14-bit, 1 GSPS ADC (ADC). The device contains on-chip buffer and sample and hold circuit designed for low power consumption, small size and ease of use and design. The device is designed for up to 2 GHz wideband analog signal is sampled. AD9690 for wide input bandwidth, high sampling rate, excellent linearity and low power consumption and small package optimized.
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Size: 2195456 |
Author: 张艺兴 |
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