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[Other] SC-DSC

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术，就是不增加多余度而扰乱信号，改变数字信号的统计特性，使其近 似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序 列（伪随机序列）理论之上的。解扰是加扰的逆过程，恢复原始的数字信号。 如果数字信号具有周期性，则信号频谱为离散的谱线，由于电路的非线 性，在多路通信系统中，这些谱线对相邻信道的信号造成串扰。而短周期信号 经过扰码器后，周期序列变长，谱线频率变低，产生的非线性分量落入相邻信 道之外，因此干扰减小。 在有些数字通信设备中，从码元“0”和“1”的交变点提取定时信息，若 传输的数字信号中经常出现长的“1”或“0”游程，将影响位同步的建立和保 持。而扰码器输出的周期序列有足够多的“0”、“1”交变点，能够保证同步 定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[VHDL-FPGA-Verilog] CPLD_raoma

Description: 基于CPLD的扰码与解扰码器的设计，扰码用M序列实现，m序列级数和频率可选-CPLD based on the scrambling code and Descrambling codec design, scrambling code sequence with M realize, m sequence of series and frequency optional
Platform: | Size: 39936 | Author: 梁奔山 | Hits:

[Embeded-SCM Develop] pcie_vera_tb_latest.tar

Description: FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs -FEATURES • 16 bit PIPE Spec PCI Express Testbench • Link training • Initial Flow Control • Packet Classes for easy to build PHY,DLLP and TLP packets • DLLP 16 bit CRC and TLP LCRC generation • Sequence Number generation and checking • ACK TLP packets • Scrambling • MemRd MemWr CfgRd CfgWr TLPs
Platform: | Size: 169984 | Author: Arun | Hits:

[VHDL-FPGA-Verilog] scramble

Description: 通信用加扰码VHDL电路，解决光传输过程中的连零和连一码的出现。-Communication scrambling circuit VHDL Code
Platform: | Size: 1024 | Author: 江山 | Hits:

[VHDL-FPGA-Verilog] CCPCH_DPCH

Description: WCDMA扰码识别，VHDL语言编写-WCDMA scrambling code identification, VHDL language
Platform: | Size: 152576 | Author: 阿甘 | Hits:

[Crack Hack] Logistichecat

Description: 将猫映射(cat map ) 与Logist ic 映射相结合, 构造了一种语音加密算法. 该算法首先将语音数据堆叠成二维, 然后利用二维猫映射将数据的位置置乱, 最后利用一维Logist ic 映射构造替换表, 对数据进行扩散.-The cat map (cat map) and Logist ic mapping the combination of a voice encryption algorithm is constructed. The algorithm first voice data stacked into two-dimensional, and then use two-dimensional cat map the location of the data scrambling and finally the use of one-dimensional Logist ic mapping structure to replace the table, the data spread.
Platform: | Size: 388096 | Author: 刘非 | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: 该系统通过顶层模块，调用7底层模块实现。7大模块底层模块为：理想信源数据接收模块，理想信源数据缓存模块，LAPS成帧模块，加扰并发送LAPS帧模块，接收LAPS帧并解扰模块，接收LAPS帧数据缓存模块，解帧并发送数据给理想信源模块。另，还有一个fifo模块，以便两个缓存模块调用。-The system top-level module, called 7, the bottom module. Bottom-7 module module: the ideal source of data receiver module, an ideal source of data cache module, LAPS framing module, scrambling and send LAPS frame module, receiving and descrambling module LAPS frame, receive LAPS frame data buffer module, solution frame and sending data to a good source module. The other, there is a fifo module to call the two cache modules.
Platform: | Size: 6144 | Author: mao | Hits:

[VHDL-FPGA-Verilog] QPSK

Description: qpsk调制的vhdl程序 扩频 加扰 解扩 解扰-the qpsk vhdl program spread spectrum modulation scrambling despreading descrambling
Platform: | Size: 2048 | Author: lp | Hits:

[VHDL-FPGA-Verilog] jiarao4

Description: 加扰与解扰，VHDL实现。初始寄存器值为1产生的m序列。-Scrambling and descrambling, VHDL. Initial register value 1 of the m-sequences generated.
Platform: | Size: 1854464 | Author: 杨超 | Hits:

[VHDL-FPGA-Verilog] test_scramb

Description: VHDL编写加扰和解扰程序，程序连在一起仿真正确，并通过下板子抓数据验证程序没问题-Write scrambling and descrambling program, VHDL program together properly simulation, and data validation procedures is caught by the board no problem
Platform: | Size: 1440768 | Author: 杨超 | Hits:

[DSP program] scramblingadescrambling-vhdl

Description: scrambling and descrambling
Platform: | Size: 12288 | Author: hebbar | Hits:

[VHDL-FPGA-Verilog] sin

Description: 用VHDL语言编写实现以下功能：用PLL，复位器，分频器，同步时钟，计数器来产生正弦波，再在其上加扰，用FIR滤波器进行滤波整形，最后得到输出。-Using VHDL language to achieve the following functions: PLL, reset, clock synchronization, frequency divider, counter to generate sine wave, and then scrambling on the filter shaping filter with FIR, finally get the output.
Platform: | Size: 6779904 | Author: 猪头 | Hits:

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