Search - segment vhdl

Search - segment vhdl - List

[VHDL-FPGA-Verilog] S3Demo DL : 0: Spartan 3 Digilent Demo:This demo drives the perphrials on the Spartan 3 board. This drives a simple pattern to the VGA port, connects the switches to the LEDs, buttons to each anode of the seven segment decoder. The seven segment decoder has a simple counter running on it, and when SW0 is in the up position the seven segment decoder will display scan codes from the PS2 port. This demo how ever does not drive the RS-232 port or the memory. This is a simple design done entirely VHDL not microblaze.
Update : 2025-02-17 Size : 714kb Publisher : Roy Hsu
[Linux-Unix] qiduan DL : 0: 七段数码管显示程序，用VHDL语言编译的-Seven-Segment LED display program, compiled using VHDL language
Update : 2025-02-17 Size : 423kb Publisher : 史乐
[File Format] deng DL : 0: verilogHDL跑马灯程序，主要是七段译码显示的学习编程。-Marquee verilogHDL procedures, mainly showed that the learning Seven-Segment Decoder programming.
Update : 2025-02-17 Size : 1kb Publisher : 王义
[VHDL-FPGA-Verilog] 7led DL : 0: 一个最大公约数七段显示器编码VHDL代码设计-Seven-Segment display a common denominator coding VHDL code design
Update : 2025-02-17 Size : 3kb Publisher : linew
[VHDL-FPGA-Verilog] VHDLjindianshili DL : 0: 37个经典的VHDL程序。有比较器、七段译码器、状态机等。-37 classic VHDL procedures. Have comparators, Seven-Segment decoder, such as state machines.
Update : 2025-02-17 Size : 39kb Publisher : kcamellia
[VHDL-FPGA-Verilog] work3CNT4BDECL7S DL : 0: 7段数码显示译码器设计7段数码是纯组合电路，通常的小规模专用IC，如74或4000系列的器件只能作十进制BCD码译码，然而数字系统中的数据处理和运算都是二进制的，所以输出表达都是十六进制的，为了满足十六进制数的译码显示，最方便的方法就是利用译码程序在FPGA/CPLD中来实现。例子作为七段译码器，输出信号LED7S的7位分别接数码管的7个段，高位在左，低位在右。例如当LED7S输出为“1101101”时，数码管的7个段g、f、e、d、c、b、a分别接1、1、0、1、1、0、1；接有高电平的段发亮，于是数码管显示“5”。-7 digital display decoder design 7 Digital is pure combinational circuits, usually of small-scale dedicated IC, such as 74 or 4000 Series devices can only be used to decimal BCD decoder, but digital systems in the data processing and computing are binary, so the output expression are hexadecimal, and hexadecimal number in order to meet the needs of the decoding shows that the most convenient way is to use decoding process in FPGA/CPLD in to achieve. Seven-Segment decoder as an example, the output signal of the seven were LED7S access digital pipe 7 above, high in the left, low in the right. For example, when LED7S output as
Update : 2025-02-17 Size : 81kb Publisher : lkiwood
[Other] shizhong DL : 0: 用vhdl语言描述时钟的功能，并通过七段译码显示输出。-VHDL language used to describe the function of the clock and through the Seven-Segment display decoder output.
Update : 2025-02-17 Size : 66kb Publisher : wuyub
[ARM-PowerPC-ColdFire-MIPS] demo DL : 0: Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset - FLEX_PB1 Input n - FLEX_SW switches 1 to 8 Output: Countdown - two 7-segment LEDs. Done light - decimal point on Digit1. Operation: Setup the binary input n number. Press the Reset switch. See the countdown from n down to 0 on the 7-segment LEDs. Done light lit when program terminates.-Flex chip implementation File: UP2FLEX JTAG jumper settings: down, down, up, up Input: Reset- FLEX_PB1 Input n- FLEX_SW switches 1 to 8 Output: Countdown- two 7-segment LEDs. Done light- decimal point on Digit1. Operation: Setup the binary input n number. Press the Reset switch. See the countdown from n down to 0 on the 7-segment LEDs. Done light lit when program terminates.
Update : 2025-02-17 Size : 105kb Publisher : james
[Other] CLOCK DL : 0: 文通过ALTERA公司的quartus II软件，用Verilog HDL语言完成多功能数字钟的设计。主要完成的功能为：计时功能，24小时制计时显示；通过七段数码管动态显示时间；校时设置功能，可分别设置时、分、秒；跑表的启动、停止、保持显示和清除。-Through the ALTERA company quartus II software, using Verilog HDL language to complete the design of multi-function digital clock. The main function of the completion are: time function, 24-hour time display through the Seven-Segment LED dynamic display time school settings function, can be set hours, minutes, seconds the stopwatch to start, stop, and maintain display and removal.
Update : 2025-02-17 Size : 178kb Publisher : 张保平
[Communication] sfs DL : 0: DW 256 DUP(?) STACK1 ENDS DDATA SEGMENT MES1 DB The least number is:$ MES2 DB 0AH,0DH, The largest number is:$ NUMB DB 0D9H,07H,8BH,0C5H,0EBH,04H,9DH,0F9H DDATA ENDS CODE SEGMENT ASSUME CS:CODE,DS:DDATA START: MOV AX,DDATA MOV DS,AX MOV SI,OFFSET NUMB MOV CX,0008H JCXZ A4 MOV BH,[SI] MOV BL,BH A1: LODSB AL=DS:[SI],SI=SI+1 CMP AL,BH JBE A2 MOV BH,AL JMP A3 A2: CMP AL,BL JAE A3 MOV BL,AL A3: LOOP A1 A4: MOV DX,OFFSET MES1 show mes1 MOV AH,09H INT 21H MOV AL,BL show the least number AND AL,0F0H get the highest 4 bits SHR AL,4 CMP AL,0AH JB C2 ADD AL,07H C2: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV AL,BL AND AL,0FH get the lowest 4 bits CMP AL,0AH JB C3 ADD AL,07H C3: ADD AL,30H MOV DL,AL show character MOV AH,02H INT 21H MOV DX,OFFSET MES2 show mes2 MOV AH,09H INT 21H -DW 256 DUP (?) STACK1 ENDSDDATA SEGMENTMES1 DB The least number is: $ MES2 DB 0AH, 0DH, The largest number is: $ NUMB DB 0D9H, 07H, 8BH, 0C5H, 0EBH, 04H, 9DH, 0F9HDDATA ENDSCODE SEGMENT ASSUME CS: CODE, DS: DDATASTART: MOV AX, DDATA MOV DS, AX MOV SI, OFFSET NUMB MOV CX, 0008H JCXZ A4 MOV BH, [SI] MOV BL, BHA1: LODSB AL = DS: [SI], SI = SI+ 1 CMP AL, BH JBE A2 MOV BH, AL JMP A3A2: CMP AL, BL JAE A3 MOV BL, ALA3: LOOP A1A4: MOV DX, OFFSET MES1 show mes1 MOV AH, 09H INT 21H MOV AL, BL show the least number AND AL , 0F0H get the highest 4 bits SHR AL, 4 CMP AL, 0AH JB C2 ADD AL, 07H C2: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV AL, BL AND AL, 0FH get the lowest 4 bits CMP AL, 0AH JB C3 ADD AL, 07HC3: ADD AL, 30H MOV DL, AL show character MOV AH, 02H INT 21H MOV DX, OFFSET MES2 show mes2 MOV AH, 09H INT 21H
Update : 2025-02-17 Size : 1kb Publisher : 张于
[VHDL-FPGA-Verilog] freqm DL : 0: a simple implementation of a frequency meter with the BCD-counter and the 7-segment LED display
Update : 2025-02-17 Size : 12kb Publisher : wangfeng
[VHDL-FPGA-Verilog] 04_dynamic_hex2 DL : 0: This is 7-segment LED contoler in vhdl
Update : 2025-02-17 Size : 7kb Publisher : darek
[VHDL-FPGA-Verilog] VerilogHDL_code DL : 0: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Update : 2025-02-17 Size : 1.53mb Publisher : shsh
[SCM] miaobiao.RAR DL : 0: 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Update : 2025-02-17 Size : 33kb Publisher : cuipinpin
[VHDL-FPGA-Verilog] Seven-Segment-Decoder DL : 0: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Update : 2025-02-17 Size : 1kb Publisher : 吴金通
[VHDL-FPGA-Verilog] xq_Test7 DL : 0: VHDL语言编写一个BCD计数器并在七段显示数码管上显示的程序,实现了动态扫描，而且很好用-VHDL language a BCD counter and in the seven-segment display digital tube display process to achieve a dynamic scanning, and it just works
Update : 2025-02-17 Size : 141kb Publisher : 夏强
[VHDL-FPGA-Verilog] 7segmentLED DL : 0: 7段数码管显示源代码。基于VHDL语言，实现对7段数码管显示。-7 segment LED display source code. Based on the VHDL language, achieving seven segment LED display.
Update : 2025-02-17 Size : 3kb Publisher : xiaokun
[VHDL-FPGA-Verilog] VHDL-3BCD DL : 0: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Update : 2025-02-17 Size : 55kb Publisher : will li
[Software Engineering] Vhdl DL : 0: GAME.vhdl, VGA.vhdl VGA module.vhdl seven segment.vhdl
Update : 2025-02-17 Size : 11.69mb Publisher : Muzaffer
[Other] 八位数码管的动态显示VHDL程序 DL : 0: 7段数码管动态显示程序，高频动态显示多位数(7 segment digital tube dynamic display program)
Update : 2025-02-17 Size : 3kb Publisher : 凌晨四点半

« 12 3 4 5 6 7 8 9 10 »