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[VHDL-FPGA-Verilog] bunchcombinechange

Description: Verilog源代码,实现串并转换，学Verilog的不错的基本例程-Verilog source code, realize SERDES, learning Verilog good basic routines
Platform: | Size: 114688 | Author: 3060421006 | Hits:

[VHDL-FPGA-Verilog] s2p

Description:
Platform: | Size: 1024 | Author: wangdali | Hits:

[VHDL-FPGA-Verilog] auk_sdsdi

Description: 用于FPGA设计的代码（Verilog代码），在FPGA设计中的高速串并转换，时钟提取，对齐处理等功能-for FPGA design ,written by Verilog HDL the functions include SERDES , CDR and so on
Platform: | Size: 229376 | Author: 龙珠 | Hits:

[VHDL-FPGA-Verilog] SERDES

Description: 基于Verilog的串并转换器的设计与实现，采用两种不同的方案来实现串并和并串转换的功能，并用ISE软件仿真以及chipscope的调试-Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope
Platform: | Size: 785408 | Author: 陈凯 | Hits:

[VHDL-FPGA-Verilog] DK-ECP3-SERDES-010

Description: 为verilog 的SERDES 使用程序。可以实现高速串行接口数据通信，时钟还原。-Verilog program for the use of the SERDES. For high-speed serial interface data communications, clock restoration.
Platform: | Size: 6337536 | Author: fpga_cn | Hits:

[VHDL-FPGA-Verilog] ecp3pSerDes_Reset__Code

Description: ecp3 fpga verilog 复位程序 用来复位FPGA内部serdes -ecp3 fpga verilog reset procedure
Platform: | Size: 6144 | Author: daye | Hits:

[VHDL-FPGA-Verilog] LVDS

Description: 实现了LVDS的发送和接收，本例程增加了握手信号实现，没有用serdes(The sending and receiving of LVDS are realized)
Platform: | Size: 4096 | Author: E=MC2 | Hits:

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