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[Other] LED_DEMO_64X32

Description: LED 显示 的小程序主要用于获得点阵码串口通信的自己设置-LED display of small programs mainly for access to serial dot matrix codes set up their own communications
Platform: | Size: 14336 | Author: 聪 | Hits:

[SCM] carcacuprice

Description: 出租车计价器程序，采用c51编程，通过计数模式实现里程检测，通过串口模式0显示多个数码管显示。-Taximeter procedures, using C51 programming, through the counting mode of detection realize mileage, through serial port mode 0 show a number of digital tube display.
Platform: | Size: 2048 | Author: yuweiming | Hits:

[VHDL-FPGA-Verilog] RS232

Description: xilinx Sparten3E 串行通信及lcd字符显示-xilinx Sparten3E characters serial communication and lcd display
Platform: | Size: 2048 | Author: ronghy | Hits:

[VHDL-FPGA-Verilog] wumayi

Description: 研究了传统误码仪的工作原理与结构，并利用VHDL语言在FPGA芯片上模拟实现了绝大部分的传统误码仪的功能，如LCD显示驱动，串口通信驱动，误码测试，数据存储芯片驱动等功能.-Research on the traditional instrument of the working principle of error with the structure and language use of VHDL simulation in the FPGA chip realize most of the traditional instrument error function, such as the LCD display driver, serial port communication driver, error testing, data storage Chip-driven functions.
Platform: | Size: 4048896 | Author: 张杰 | Hits:

[SCM] ps2_rs232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。 -Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 196608 | Author: yuan | Hits:

[VHDL-FPGA-Verilog] RS232

Description: 本实验实现PS/2接口与RS-232接口的数据传输， PS/2键盘上按下按键，可以通过RS-232自动传送到主机的串口调试终端上（sscom32.exe）； 并在数据接收区显示接收到的字符。 串口调试终端的设置：波特率115200，一个停止位，无校验位。-Realize this experiment, PS/2 interface with RS-232 data interface, PS/2 keyboard to press the button, through RS-232 automatic transmission to the host serial debug terminal (sscom32.exe) and data receiving display received characters. Serial debug terminal settings: 115200 baud rate, one stop bit, no parity bit.
Platform: | Size: 730112 | Author: 李华 | Hits:

[SCM] Flash_ROM_lab

Description: 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct.
Platform: | Size: 3072 | Author: 劳杰勇 | Hits:

[Linux-Unix] DP_RAM_lab

Description: 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger display.
Platform: | Size: 4096 | Author: 劳杰勇 | Hits:

[VHDL-FPGA-Verilog] Exp6-VGA

Description: Create-SOPC1000X 嵌入式开发平台、用于 FGPA的 JTAG 下载电缆、VGA显示器、 串口数据线、PC主机。 -Create-SOPC1000X embedded development platform for FGPA the JTAG download cable, VGA display, serial data cable, PC host.
Platform: | Size: 662528 | Author: yangcheng | Hits:

[VHDL-FPGA-Verilog] DM7_COLR_LCD_C5T

Description: 任意信号波形采样和频谱分析演示文件 ADC信号采样、RS232串行通信和频谱分析 增加ADC采样控制模块，接上ADC，即可把模拟信号采入PC机上显示，和相应的频谱分析。 -Arbitrary signal waveforms and spectral analysis of the sampling ADC signal sample presentation, RS232 serial communication and increase the ADC sampling frequency spectrum analysis control module, connected to ADC, the analog signal can take into the PC, display, and the corresponding spectral analysis.
Platform: | Size: 41984 | Author: 邢旭 | Hits:

[VHDL-FPGA-Verilog] 232

Description: 实现PS/2接口与RS-232接口的数据传输， 可以通过RS-232自动传送到主机的串口调试终端上并在数据接收区显示接收到的字符。-The realization of PS/2 port RS-232 interface with data transfer, RS-232 can be automatically sent to the host serial debug terminal and reception area in the data display received characters.
Platform: | Size: 15360 | Author: 包宰 | Hits:

[Embeded-SCM Develop] altera-schemic-

Description: FPGA应用，Altera的FPGA开发板原理图汇集，FPGA最小系统，rs232串口转换，VGA显示-FPGA applications, Altera' s FPGA development board schematic pooling, FPGA minimum system, rs232 serial converter, VGA display etc.
Platform: | Size: 1720320 | Author: 吴贵锋 | Hits:

[VHDL-FPGA-Verilog] serial

Description: 该程序用vhdl 编写，模拟串口工作，对上位机发送数据在串口调试工具下显示，接受上位机数据在数码管上显示-Vhdl prepared to use the program to simulate the serial port work, send data to the PC serial port debug tools in the next showed that IPC data in digital tube display
Platform: | Size: 3072 | Author: gjp_rain | Hits:

[VHDL-FPGA-Verilog] dianyabiao

Description: 基于ISD4004的语音报值交直流电压表的设计：本文介绍了基于语音芯片ISD4004的语音报值交直流电压表的设计。电路由数据采集部分，A/D转换部分，键盘与显示部分，单片机控制部分，语音报值部分和扩展功能部分组成。电路使用了并行与串行总线相结合的方式，使设计与编程灵活简便。创意新颖有趣，富于人性化，避免了频繁观察仪器显示之苦，对减轻工程技术人员的工作量和提高工作效率现实意义。-ISD4004 voice-based value of AC and DC voltage at the design table: In this paper, based on the voice chip ISD4004 voice at the value of AC-DC voltage meter design. Part by the data acquisition circuit, A/D conversion of part of the keyboard and display, single-chip control of the reported value of part of speech and expand the functional parts. The use of a parallel circuit with a combination of serial bus, so as to enable convenient and flexible design and programming. Innovative ideas interesting and full of humanity, to avoid the frequent observation shows that the hardship of equipment, engineering and technical personnel to reduce workload and improve the efficiency of practical significance.
Platform: | Size: 475136 | Author: song | Hits:

[VHDL-FPGA-Verilog] uart

Description: 程序说明: 本次实验控制开发板上面的串口，与PC机进行通信，并在串口精灵里面显示字符。 目录说明: 工程在\project文件夹里面 源文件和管脚分配在\rtl文件夹里面 下载文件在\download文件夹里面,.mcs为PROM模式下载文件,.bit为JTAG调试下载文件。-Procedure Note: The experimental control development board above the serial port to communicate with the PC machine, and the serial wizard inside the display characters. Catalog Description: The project \ project folder inside the source file and pins distributed in \ rtl folder inside download the file in the \ download folder inside,. Mcs for the PROM mode download files,. Bit for the JTAG debug download the file.
Platform: | Size: 905216 | Author: 军军 | Hits:

[Software Engineering] CPLD_KEYBOARD

Description: 本设计是用VHDL语言来实现的基于RS232按位串行通信总线的行列式矩阵键盘接口电路，具有复位和串行数据的接收与发送功能，根据发光二极管led0—led2的显示状态可判断芯片的工作情况；实现所有电路功能的程序均是在美国 ALTERA公司生产的具有现场可编程功能的芯片EPM7128SLC84-15上调试通过的。该电路的设计贴近生活，实用性强，制成芯片后可作为一般的PC机键盘与主机的接口使用。 -The design is based on VHDL language to achieve bit serial RS232 communication bus according to the determinant of matrix keyboard interface circuit with a reset, and serial data reception and transmission capabilities, according to light-emitting diode display led0-led2 status can be judged chip work to achieve all the circuit functions of the program are produced in the United States has ALTERA Field Programmable functions EPM7128SLC84-15 on-chip debug passed. The circuit design of daily life, practical, post-produced chips can be used as a general PC, the keyboard and the host interface.
Platform: | Size: 67584 | Author: jalon | Hits:

[VHDL-FPGA-Verilog] 6

Description: 4位数码扫描显示电路,我们控制一个七段LED需要8个输出端口；如果要输出四位十进制数，就需要32的输出端口，这将占用大量的端口资源。采用串行扫描显示，我们只需要8+4共12个端口即可。其原理是：用一个四位的输出端控制，某一时刻只选中其中的一个LED（输出为‘1’表示选中），八位的输出端将该LED所需要显示的值输出；然后四位的输出端值改变，选中下一个LED。这样依次类推。如果选择的频率很快，达到50Hz以上，由于人眼的视觉暂留效应，看起来就像4个LED同时显示。 设计一个程序，输入四个一位十进制数，用4个LED显示出来。CLK采用频率可调信号发生器，逐渐改变频率，观察扫描频率的改变对输出效果的影响。 输入：连续脉冲，逻辑开关；输出：七段LED。 -4 digital scanning display circuit, we need to control a seven-segment LED output port 8 If you want to output four decimal numbers, you need the output port 32, which will take up a lot of ports. Serial scans showed, we need only 8 of 12 ports can be+4. The principle is: the output of four with a control, a time to select only one LED (output 1 is selected), 8 output of the LED by the need to show the value of the output then The output value of the four changes, select the next LED. This and so on. If you select the frequency rapidly, reaching more than 50Hz, as the human eye s persistence of vision effect, looks like a 4 LED display simultaneously. Design a program, enter a decimal number four, with four LED display. CLK signal generator with adjustable frequency, gradually changing the frequency of observed changes in scan frequency effect on the output. Input: Continuous pulse, logic switches output: seven-segment LED.
Platform: | Size: 4096 | Author: 李小勇 | Hits:

[VHDL-FPGA-Verilog] VHDL-based-design-of-SPI

Description: 基于VHDL的串行同步通信SPI设计 本设计是用Quartus作为开发环境，以DE2板为硬件平台实现的SPI同步串行通讯。设计过程方便。根据接收和发送两个主要部分实现了SPI的基本功能。此外，该设计还实现了波特率发生器，数码管显示的功能。用DE2板实现具有电路简洁，开发周期短的优点。充分利用了EDA设计的优点。开发过程用了VHDL硬件描述语言进行描述，从底层设计，分模块进行，充分提高了设计者的数字逻辑设计的概念。-VHDL-based SPI serial synchronous communication design as the design is the use of Quartus development environment to DE2 board as the hardware platform of the SPI synchronous serial communication. Facilitate the design process. According to both send and receive SPI implements the main part of the basic functions. In addition, the design also implements the baud rate generator, digital display features. DE2 board to achieve a circuit with a simple, short development cycle advantages. Full use of the EDA design advantages. Development Process VHDL hardware description language used to describe the design from the ground, sub-module, to fully enhance the designer' s concept of digital logic design.
Platform: | Size: 51200 | Author: 陈添 | Hits:

[VHDL-FPGA-Verilog] lcdasegaled

Description: lcd显示 跑马灯显示 七段数码管计时 12232F是一种内置8192个16*16点汉字库和128个16*8点ASCII字符集图形点阵液晶显示器,它主要由行驱动器/ 列驱动器及128×32全点阵液晶显示器组成。可完成图形显示,也可以显示7.5×2个(16×16点阵)汉字.与外部CPU接口采用并行或串行方式控制。-lcd display Seven-Segment LED Display Marquee is a built-in timing 12232F 8192 16* 16 points and 128 Chinese character library 16* 8 ASCII character set dot matrix liquid crystal display, which is mainly from the line driver/line driver and 128 × 32 full dot matrix liquid crystal display components. Complete graphical display can also show 7.5 × 2 个 (16 × 16 dot) character. And the external CPU interface with parallel or serial control.
Platform: | Size: 1107968 | Author: wws | Hits:

[VHDL-FPGA-Verilog] VHDL-Responder-Course-Design

Description: 开始键按下后，8个进度指示灯依次点亮，之后开始抢答。4个按键开关代表4个抢答键，由数码管显示最先按下的开关序号，表示此号码抢答成功。若在进度灯全亮之前有任意键被按下，则表示有人犯规！系统结构描述：此系统共包括4个板块，分别是输入板块、计数器板块、数码显示器板块、判断板块，各功能组合一起构成一个完整的抢答器。-Start key is pressed, 8 progress lights were lit, and then answer in the beginning. 4 key switches on behalf of four answer in key pressed by the digital display the switch serial number first, that this number Responder success. If the light all light in the progress before the any key is pressed, it means that some foul! System Architecture Description: This system includes a total of 4 sections, namely the input plate, counter plate, digital display board, determine the plate, the combination of features together constitute a complete Responder.
Platform: | Size: 373760 | Author: 竹下寺宁 | Hits:
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