Description: 标准的异步串口通讯设计程序——基于VHDL编程-communication design programme of standard asynchronous serial port base on VHDL programme Platform: |
Size: 10240 |
Author:于飞 |
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Description: 用VHDL实现串口 可以实现与pc机的通信 收发 中断都可以 效果比较好-VHDL implement serial port, it can communicate with pc, it can accept and send message, and it can be interrupted. Platform: |
Size: 9216 |
Author:熊明 |
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Description: uart d的verilog 程序，可以实现普通串口功能-UART d Verilog procedures can be achieved ordinary serial port function Platform: |
Size: 5120 |
Author:梁启 |
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Description: 这是我最近买的一套CPLD开发板VHDL源程序并附上开发板的原理图,希望对你是一个很好的帮助!其中内容为:8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟.-which I have recently bought a CPLD Development Board VHDL source code accompanied the development of the plate diagram, You hope to be a good help! which states : eight priority encoder, multipliers, multi-path selectors, BCD binary switch, adder, subtraction device, the simple state machine, four comparators, seven of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng, traffic lights, Digital Clock. Platform: |
Size: 4642816 |
Author:Jawen |
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Description: 朋友，我是Jawen.看到先前上载的一套CPLD开发板的VHDL源码挺受欢迎的，现在就将她的Verilog源码也一并贡献给大家：8位优先编码器,乘法器,多路选择器,二进制转BCD码,加法器,减法器,简单状态机,四位比较器,7段数码管,i2c总线,lcd液晶显示,拨码开关,串口,蜂鸣器,矩阵键盘,跑马灯,交通灯,数字时钟-friends, I Jawen. previously seen on the set of CPLD Development Board VHDL source code quite welcome, Now she will also be Verilog source contribution to everyone : eight priority encoder, multipliers, Multi-channel selector, binary to BCD, adder, subtraction device, the simple state machine, four comparators, 7 of the digital control, i2c bus, lcd LCD allocated code switches, serial port, the buzzer sounded, matrix keyboards, Bomadeng. Traffic lights, digital clock Platform: |
Size: 3151872 |
Author:Jawen |
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Description: 出租车计价器程序，采用c51编程，通过计数模式实现里程检测，通过串口模式0显示多个数码管显示。-Taximeter procedures, using C51 programming, through the counting mode of detection realize mileage, through serial port mode 0 show a number of digital tube display. Platform: |
Size: 2048 |
Author:yuweiming |
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Description: SPI(serial port interface)的Verilog/VHDL源代碼，已模擬並驗證。-SPI (serial port interface) of the Verilog/VHDL source code, has been simulated and verified. Platform: |
Size: 116736 |
Author:hcjian |
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Description: 以cyclone系列的EP2C5Q208为核心的实验板程序.包括流水灯,I2C存储器.SPI存储器,数码管,串口,LCD等-Cyclone in series as the core EP2C5Q208 experimental procedure. Including water lights, I2C memory. SPI memory, digital control, serial port, LCD, etc. Platform: |
Size: 2980864 |
Author:sarah |
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Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在
--PC机上安装一个串口调试工具来验证程序的功能。
-- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控
--制器，10个bit是1位起始位，8个数据位，1个结束
--位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实
--现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是
--9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间
--划分为8个时隙以使通信同步.
--程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome"
--字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制
--数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at
- PC machine on the installation of a serial debugging tools to verify the function of the procedure.
- Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control
- System, and 10 bit is a start bit, 8 data bits, 1 Ending
- Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real
- Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are
- 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time
- Is divided into eight time slots in order to enable synchronous communication.
- Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome"
- String (serial debug tools is set to accept by way of A Platform: |
Size: 65536 |
Author:johnson |
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Description: 用SmartGen生成一个256*8的大小同步FIFO，并通过串口发送数据初始化FIFO。然后，再通过串口返回到上位机的串口调试程序显示，确认数据是否正确。-SmartGen generated with a size of 256* 8 Synchronous FIFO, and sending data through the serial port to initialize FIFO. And then back through the serial port to the PC serial port debugger display to confirm the data is correct. Platform: |
Size: 3072 |
Author:劳杰勇 |
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Description: 用SmartGen 生成一个2k*8 Dual Port RAM，并通过串口发送数据初始化RAM。然后通过串口返回到上位机的串口调试程序显示。-SmartGen generated using a 2k* 8 Dual Port RAM, and sending data through the serial port to initialize RAM. And back through the serial port to the PC serial port debugger display. Platform: |
Size: 4096 |
Author:劳杰勇 |
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Description: 串口通信的概念非常简单，串口按位（bit）发送和接收字节。尽管比按字节（byte）的并行通信慢，但是串口可以在使用一根线发送数据的同时用另一根线接收数据。它很简单并且能够实现远距离通信。比如IEEE488定义并行通行状态时，规定设备线总常不得超过20米，并且任意两个设备间的长度不得超过2米；而对于串口而言，长度可达1200米。典型地，串口用于ASCII码字符的传输。通信使用3根线完成：（1）地线，（2）发送，（3）接收。由于串口通信是异步的，端口能够在一根线上发送数据同时在另一根线上接收数据。其他线用于握手，但是不是必须的。串口通信最重要的参数是波特率、数据位、停止位和奇偶校验。-The concept of serial communication is very simple, serial by bit (bit) to send and receive bytes. Although more than by byte (byte) of parallel communication slow, but can use a serial line to send data at the same time another line to receive data. It is very simple and can achieve long-distance communications. For example, the definition of IEEE488 parallel access mode, the total line often provides equipment shall not be more than 20 meters, and between any two devices may not be more than two meters in length and in terms of the serial port, up to 1200 meters in length. Typically, serial code for the ASCII character transmission. 3 lines of communication to use to complete: (1) ground, (2) send, (3) to receive. Due to the asynchronous serial communication port to send data in a line at the same time another line to receive data. Other lines for the handshake, but not necessary. Serial communication the most important parameter is the baud rate, data bits, stop bits and parity.
Platform: |
Size: 1024 |
Author:zhendongzhao |
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Description: 基于FPGA的串口发送程序，用VHDL语言编写，采用状态机的方法，可用串口调试软件进行测试-FPGA-based serial port procedures, using VHDL language, using the state machine approach can be used to test serial debugging software Platform: |
Size: 1024 |
Author:yyc |
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