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Search - seven segment vhdl code

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[VHDL-FPGA-Verilog] 7led

Description: 一个最大公约数七段显示器编码VHDL代码设计-Seven-Segment display a common denominator coding VHDL code design
Platform: | Size: 3072 | Author: linew | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_code

Description: 几个常用的接口实验的程序代码，用Verilog HDL语言编写的，包括七段数码管、拨码开关、蜂鸣器、矩阵键盘、串口、I2C、跑马灯等。-Some commonly used experimental procedures for the interface code, using Verilog HDL language, including Seven-Segment LED, DIP switch, buzzer, matrix keyboard, serial, I2C, marquees, etc..
Platform: | Size: 1603584 | Author: shsh | Hits:

[SCM] miaobiao.RAR

Description: 实验采用七段码LED设计（数码管），显示直观；采用定时器中断，计时更准确；功能齐全，可随时启动、停止、清零，后者智能化程度更高。-Seven-Segment LED code using the experimental design (digital control), visual display using timer interrupt, a more accurate time functions, may at any time to start, stop, cleared, and the latter an even higher degree of intelligence.
Platform: | Size: 33792 | Author: cuipinpin | Hits:

[VHDL-FPGA-Verilog] qiduan

Description: EDA 七段译码器 VHDL代码-EDA Seven-Segment Decoder VHDL code
Platform: | Size: 1024 | Author: 啊毛 | Hits:

[VHDL-FPGA-Verilog] qiduan

Description: 用vhdl语言实现按键操控多个七段码控制-Vhdl language with control buttons to control a number of Seven-Segment Code
Platform: | Size: 142336 | Author: 邢旭 | Hits:

[VHDL-FPGA-Verilog] VHDLCODE

Description: VHDL的一些典型源代码，有七段数码管译码器，格雷码转换为二进制码，八位数字比较器等等。-Typical VHDL source code, there are Seven-Segment LED Decoder, Gray code is converted to binary code, the eight figures and so on.
Platform: | Size: 160768 | Author: 李军 | Hits:

[VHDL-FPGA-Verilog] Seven-Segment-Decoder

Description: 用VHDL语言在FPGA上实现将十进制bcd码转换成七段led显示码-FPGA using VHDL language to achieve will be converted to decimal bcd yards led seven segment display code
Platform: | Size: 1024 | Author: 吴金通 | Hits:

[VHDL-FPGA-Verilog] 7segmentLED

Description: 7段数码管显示源代码。基于VHDL语言，实现对7段数码管显示。-7 segment LED display source code. Based on the VHDL language, achieving seven segment LED display.
Platform: | Size: 3072 | Author: xiaokun | Hits:

[VHDL-FPGA-Verilog] seven

Description: 基于VHDL实现输入控制7段数码管的代码，分别用逻辑表达式法和真值表法实现。-VHDL-based implementation of digital control input control 7-segment code, respectively, a logical expression method and truth table method to achieve.
Platform: | Size: 1024 | Author: cckaa | Hits:

[VHDL-FPGA-Verilog] VHDLseven-segmentdecoder

Description: VHDL在液晶显示上的七段译码器源码,应用于FPGA,ASIC等硬件设计-VHDL in the seven-segment liquid crystal display on the decoder source code, used in FPGA, ASIC and other hardware design
Platform: | Size: 1024 | Author: qianli | Hits:

[VHDL-FPGA-Verilog] 2

Description: BCD码七段译码器CC4511,用VHDL语言来描述CC4511。-BCD code seven-segment decoder CC4511, using VHDL language to describe the CC4511.
Platform: | Size: 2048 | Author: 李小勇 | Hits:

[VHDL-FPGA-Verilog] CLOCK

Description: Clcok Source Code in VHDL fo FPGA Devices, Display Time in Seven Segment
Platform: | Size: 958464 | Author: saber | Hits:

[VHDL-FPGA-Verilog] verilog_calculator

Description: 用verilog编写的简易计算器代码。通过一位全加器组成电路，可以实现加法、减法和乘法，并在七段数码管上显示出十进制的结果。-Simple calculator with code written in verilog. Composed by a full adder circuit, can add, subtract and multiply, and in the seven-segment LED display on the decimal result.
Platform: | Size: 16384 | Author: 刘涛 | Hits:

[VHDL-FPGA-Verilog] jishuqi

Description: 带计数使能、异步复位、带进位输出的增1六位二进制计数器，计数结果由共阴极七段数码管显示。用VHDL源代码描述-With count enable, asynchronous reset, brought by a six-bit output of the binary counter, counting the results from the common cathode seven segment LED display. Described with the VHDL source code
Platform: | Size: 10240 | Author: 小杰 | Hits:

[Software Engineering] vhdl-7Nixie-tube

Description: vhdl 七段数码管代码 可以把代码转换成可以在七段数码管上显示的代码-Seven-Segment LED vhdl code into the code can be displayed in seven sections of the code on the digital
Platform: | Size: 4096 | Author: zhaohong | Hits:

[VHDL-FPGA-Verilog] bin2bcd7seg

Description: 用vhdl语言编译一个码制转换 四位二进制->BCD码，然后将BCD码->七段显示器码。 （1）当输入为0~9的数时，其十位数为0，个位数=输入。 当输入为10~15的数时，其十位数为1，个位数=输入-10。 （2）然后将十位和个位的BCD码转换为七段显示码 -Vhdl language used to compile a binary code system conversion of four-> BCD code, then BCD code-> seven-segment display code. (1) When the input is a number from 0 to 9, its ten digits 0 digits = input. When the input is 10 to 15 the number, the tens digit is 1, digits = input-10. (2) and then ten and a bit BCD code is converted to seven segment display code
Platform: | Size: 326656 | Author: 宋子皓 | Hits:

[VHDL-FPGA-Verilog] VHDL-3BCD

Description: 3位BCD码的计数显示电路。BCD码计数电路从0计到9然后返回到0从新计数。3位BCD码计数器可以实现从0到999的十进制计数。要将计数过程用七段显示LED数码管显示出来，这里采用动态分时总线切换电路对数码管进行扫描，对数码管依次分时选中进行输出计数的个、十、百位的数据。-3 BCD code count display circuit. BCD code counting circuit count from 0 to 9 and then back to 0 from the new count. 3 BCD code counter can be achieved from 0 to 999 decimal count. Counting process with seven segment displays to LED digital tube displays, where dynamic time-sharing digital bus switch circuit to scan, followed by time-sharing of digital output selected for a count of ten, hundred bits of data.
Platform: | Size: 56320 | Author: will li | Hits:

[VHDL-FPGA-Verilog] vhdl-program-for-seven-segment-display

Description: seven segment code using vhdl
Platform: | Size: 1024 | Author: chhavi | Hits:

[VHDL-FPGA-Verilog] Multi-function-digital-clock

Description: 1、 了解数字钟的工作原理。 2、 进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、 掌握VHDL编写中的一些小技巧。 -1, to understand digital clock works. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
Platform: | Size: 1594368 | Author: | Hits:

[VHDL-FPGA-Verilog] Digital-stopwatch

Description: 1、了解数字秒表的工作原理。 2、进一步熟悉用VHDL语言编写驱动七段码管显示的代码。 3、掌握VHDL编写中的一些小技巧。 -1, to understand the working principle of digital stopwatch. 2, more familiar with the use of VHDL language driver seven segment display code. 3, master VHDL prepared some of the tips.
Platform: | Size: 1602560 | Author: | Hits:
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