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[VHDL-FPGA-Verilogsha-1

Description: 本算法基于leon2协处理器接口标准,内含testbench,在modelsim中仿真通过,在ise9.2中综合及后仿真通过。-The algorithm is based on the leon2 co-processor interface standard, including testbench, ModelSim simulation in the adoption, in ise9.2 integrated and adopted after the simulation.
Platform: | Size: 15360 | Author: ninghuiming | Hits:

[VHDL-FPGA-VerilogHASH-code-implementation-using-VHDL

Description: implementation for Secure Hash Algorithm 1 SHA-1 in vhdl language contain no test file.
Platform: | Size: 14336 | Author: waleed | Hits:

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