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[VHDL-FPGA-Verilog] spi

Description: VHDL实现SPI功能源代码 -- The SPI bus is a 3 wire bus that in effect links a serial shift -- register between the "master" and the "slave". Typically both the -- master and slave have an 8 bit shift register so the combined -- register is 16 bits. When an SPI transfer takes place, the master and -- slave shift their shift registers 8 bits and thus exchange their 8 -- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
Platform: | Size: 65536 | Author: 阿飞 | Hits:

[VHDL-FPGA-Verilog] shift_register

Description: -- DESCRIPTION : Shift register -- Type : univ -- Width : 4 -- Shift direction: right/left (right active high) -- -- CLK active : high -- CLR active : high -- CLR type : synchronous -- SET active : high -- SET type : synchronous -- LOAD active : high -- CE active : high -- SERIAL input : SI-- DESCRIPTION: Shift register- Type: univ- Width: 4- Shift direction: right/left (right active high )---- CLK active: high- CLR active: high- CLR type: synchronous-- SET active: high- SET type: synchronous- LOAD active: high- CE active: high- SERIAL input: SI
Platform: | Size: 1024 | Author: sanshanchuns | Hits:

[VHDL-FPGA-Verilog] LPT

Description: 实现开漏输出的并口，支持3.3V或5V，支持FPGA 的PS 配置功能。8位配置数据 自动移位输出，输入时钟24MHz，产生1MHz配置时钟。8位CPU数据总线接口， 11位地址总线。支持IO 的置位清除功能。-The realization of open-drain output of the parallel port, support 3.3V or 5V, support for FPGA configuration of the PS function. 8-bit configuration data automatically shift output, input clock 24MHz, resulting 1MHz clock configuration. 8-bit CPU data bus interface, address bus 11. IO-bit support for the home clearance.
Platform: | Size: 2048 | Author: tianrongcai | Hits:

[VHDL-FPGA-Verilog] barrel_shifter

Description: VHDL实现的桶型移位器，能在一个时钟周期实现对数据的（0－12位）算术右移-VHDL implementation of a barrel—shifter, able to achieve at one clock cycle of data (0-12 bit) Arithmetic Shift Right
Platform: | Size: 1024 | Author: 过时无双 | Hits:

[Windows Develop] T3_1

Description: 一个4比特移位寄存器,活跃在不断上升的边缘的时钟。登记应能转移左、右移,接受连续剧和平行(负荷)输入,而有一个异步预设(“1111”)和清晰的(“0000”)的能力。-a 4-bit shift register which is active on the rising edge of the clock. The register should be able to shift left, shift right, accept a serial and parallel (load) input, and have an asynchronous preset (“1111”) and clear(“0000”) capability.
Platform: | Size: 26624 | Author: sunzhongyuan | Hits:

[VHDL-FPGA-Verilog] par_serial-and-serial_par-VHDL

Description: 并入串出移位寄存器和8路并行输出串行移位寄存器的VHDL代码，经Quartus II 5.1验证可用-String into a shift register and 8-way parallel output serial shift register of the VHDL code, the Quartus II 5.1 can be used to verify
Platform: | Size: 1024 | Author: 随风 | Hits:

[VHDL-FPGA-Verilog] shift

Description: 用VHDL实现一个移位寄存器，是初学者需要掌握的一个简单的程序写法-Using VHDL realization of a shift register is available for beginners need a simple program written
Platform: | Size: 288768 | Author: 波波 | Hits:

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